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LTC1142-ADJ Datasheet(PDF) 9 Page - Linear Technology |
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LTC1142-ADJ Datasheet(HTML) 9 Page - Linear Technology |
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9 / 20 page  9 LTC1142/LTC1142L/LTC1142HV OPERATIO Refer to Functional Diagram As the load current increases, the output voltage de- creases slightly. This causes the output of the gain stage [Pin 27(13)] to increase the current comparator thresh- old, thus tracking the load current. The sequence of events for Burst Mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. When the output voltage is at or above the desired regulated value, the P-channel MOSFET is held off by comparator V and the timing capacitor continues to discharge below VTH1. When the timing capacitor discharges past VTH2, voltage compara- tor S trips, causing the internal sleep line to go low and the N-channel MOSFET to turn off. The circuit now enters sleep mode with both power MOSFETs turned off. In sleep mode a majority of the circuitry is turned off, dropping the quiescent current from 1.6mA to 160 µA (for one regulator block). The load current is now being supplied from the output capacitor. When the output voltage has dropped by the amount of hysteresis in comparator V, the P-channel MOSFET is again turned on and this process repeats. To avoid the operation of the current loop interfering with Burst Mode operation, a built-in offset VOS is incorporated in the gain stage. This prevents the current comparator threshold from increasing until the output voltage has dropped below a minimum threshold. To prevent both the external MOSFETs from ever being turned on at the same time, feedback is incorporated to sense the state of the driver output pins. Before the NDrive output can go high, the PDrive output must also be high. Likewise, the PDrive output is prevented from going low while the NDrive output is high. Using constant off-time architecture, the operating fre- quency is a function of the input voltage. To minimize the frequency variation as dropout is approached, the off-time controller increases the discharge current as VIN drops below VOUT + 1.5V. In dropout the P-channel MOSFET is turned on continuously (100% duty cycle) providing low dropout operation with VOUT ~ VIN. The basic LTC1142 application circuit is shown in Figure 1. External component selection is driven by the load requirement and begins with the selection of RSENSE. Once RSENSE is known, CT and L can be chosen. Next, the power MOSFETs and D1 are selected. Finally, CIN and COUT are selected and the loop is compensated. Since the 3.3V and 5V sections in the LTC1142 are identical and similarly section 1 and section 2 in the LTC1142HV-ADJ/ LTC1142L-ADJ are identical, the process of component selection is the same for both sections. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 20V. RSENSE Selection for Output Current RSENSE is chosen based on the required output current. The LTC1142 current comparators have a threshold range which extends from a minimum of 25mV/RSENSE to a maximum of 150mV/RSENSE. The current comparator threshold sets the peak of the inductor ripple current, APPLICATIO S I FOR ATIO yielding a maximum output current IMAX equal to the peak value less half the peak-to-peak ripple current. For proper Burst Mode operation, IRIPPLE(P-P) must be less than or equal to the minimum current comparator threshold. Since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., IRIPPLE(P-P) = 25mV/RSENSE (see CT and L Selection for Operating Frequency section). Solving for RSENSE and allowing a margin for variations in the LTC1142 and external component values yields: RSENSE MAX = 100mV I A graph for Selecting RSENSE vs Maximum Output Current is given in Figure 2. The load current below which Burst Modeoperation com- mences, IBURST, and the peak short-circuit current ISC(PK), |
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