UPD75516GF-079 datasheet(9/70 Pages) NEC

Part #	UPD75516GF-079

Description	4-BIT SINGLE-CHIP MICROCOMPUTER

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Manufacturer	NEC [NEC]

Direct Link	http://www.nec.com/

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9 / 70 page

9

µPD75516

4.2

NON-PORT PINS

Dual-

Function Pin

Pin Name

I/O

After Reset

Input / Output

Circuit Type *

Function

TI0

PTO0

PCL

BUZ

SCK0

SO0/SB0

SI0/SB1

INT4

INT0

INT1

INT2

KR0 to KR3

KR4 to KR7

SCK1

SO1

SI1

AN0 to AN3

AN4 to AN7

AVREF

AVSS

X1, X2

XT1

XT2

RESET

PPO

IC

VDD

VSS

Input

Output

External event pulse input pin to the timer/event counter.

Timer/event counter output pin.

B – C

E – B

F – A

F – B

M – C

B

B – C

F – C

F – A

F

E

B

Y

Y-A

Z

B

E

Clock output pin.

Fixed frequency output pin (for buzzer or system clock

trimming).

Output

Input/

output

Serial clock input/output pin.

Input/

output

Serial data output pin.

Serial bus input/output pin.

Input/

output

P13

P20

P22

P23

P01

P02

P03

P00

P10

P11

P12

P60 to P63

P70 to P73

P81

P82

P83

P150 to P153

Serial data input pin.

Serial bus input/output pin.

Edge-detected vectored interrupt input pin (valid for

detection of rising and falling edges).

Input

—

Clocked

Asynchronous

Input

—

Input

Serial falling edge detection testable input pin.

Input

Serial falling edge detection testable input pin.

Input/

output

Serial clock input/output pin.

Output

Serial data output pin.

Input

Serial data input pin.

Input

—

A/D converter analog input pin.

—

Input

—

A/D converter reference voltage input pin.

—

A/D converter reference GND potential pin.

——

Main system clock oscillation crystal/ceramic connection

pin. An external clock is input to X1 and an antiphase

clock is input to X2.

—

Input

—

Input

—

Subsystem clock oscillation crystal connection pin. An

external clock is input to XT1 and XT2 is leave open.

—

Input

—

Input

Output

—

P80

—

System reset input pin.

Timer/pulse generator pulse output pin.

—

Input

——

—

Edge-detected vectored interrupt input

pin (detected edge selection possible).

Edge-detected testable input pin (rising

edge detection).

*

Schmitt trigger inputs are circled.

—

GND potential pin.

Positive power supply pin.

Internally Connected. Connect to VSS directly.

—

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