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LTC1064CJ Datasheet(PDF) 3 Page - Linear Technology |
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LTC1064CJ Datasheet(HTML) 3 Page - Linear Technology |
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3 / 16 page  3 LTC1064 ELECTRICAL CHARACTERISTICS (Complete Filter) VS = ±5V, TA = 25°C, TTL clock input level, unless otherwise specified. The q denotes specifications which apply over the full operating temperature range. PARAMETER CONDITIONS MIN TYP MAX UNITS Center Frequency Range, fO VS = ±8V, Q ≤ 3 0.1 to 140 kHz Input Frequency Range 0 to 1 MHz Clock-to-Center Frequency LTC1064 fCLK = 1MHz, fO = 20kHz, Pin 17 High 50 ± 0.3 % Ratio, fCLK/fO LTC1064A (Note 1) Sides A, B, C: Mode 1, q 50 ± 0.8 % R1 = R3 = 5k, R2 = 5k, Q = 10, Sides D: Mode 3, R1 = R3 = 50k q 50 ± 0.9 % R2 = R4 = 5k LTC1064 Same as Above, Pin 17 Low, fCLK = 1MHz 100 ± 0.3 % LTC1064A (Note 1) fO = 10kHz Sides A, B, C q 100 ± 0.8 % Side D q 100 ± 0.9 Clock-to-Center Frequency LTC1064 fCLK = 1MHz 0.4 % Ratio, Side-to-Side Matching LTC1064A (Note 1) q 1% Clock-to-Center Frequency LTC1064 fCLK = 4MHz, fO = 80kHz, Pin 17 High 50 ± 0.6 % Ratio, fCLK/fO (Note 2) LTC1064A (Note 1) Sides A, B, C: Mode 1, VS = ±7.5V 50 ± 1.3 % R1 = R3 = 50k, R2 = 5k, Q = 5 Side D: Mode 3, R1 = R3 = 50k R2 = R4 = 5k, fCLK = 4MHz LTC1064 Same as Above, Pin 17 Low 100 ± 0.6 % LTC1064 A (Note 1) fCLK = 4MHz, fO = 40kHz 100 ± 1.3 % Q Accuracy Sides A, B, C: Mode 1, Q = 10 q ±26 % Side D: Mode 3, fCLK = 1MHz q ±38 % fO Temperature Coefficient Mode 1, 50:1, fCLK < 2MHz ±1 ppm/ °C Q Temperature Coefficient Mode 1, 100:1, fCLK < 2MHz ±5 ppm/ °C Mode 3, fCLK < 2MHz ±5 ppm/ °C DC Offset Voltage VOS1 (Table 1) fCLK = 1MHz, 50:1 or 100:1 q 215 mV VOS2 (Table 1) fCLK = 1MHz, 50:1 or 100:1 q 345 mV VOS3 (Table 1) fCLK = 1MHz, 50:1 or 100:1 q 345 mV Clock Feedthrough fCLK < 1MHz 0.2 mVRMS Maximum Clock Frequency Mode 1, Q < 5, VS ≥ ±5V 7 MHz Power Supply Current 912 23 mA q 26 mA Note 1: Contact LTC Marketing. Note 2: Not tested, guaranteed by Design. VOSN VOSBP VOSLP MODE PINS 2, 11, 14, 23 PINS 3, 10, 15, 22 PINS 4, 9, 16, 21 1VOS1 [(1/Q) + 1 + HOLP] – VOS3/Q VOS3 VOSN – VOS2 1b VOS1 [(1/Q) + 1 + (R2/R1)] – VOS3/Q VOS3 ~(VOSN – VOS2)[1 + (R5/R6)] 2VOS1 [(1 + (R2/R1) + (R2/R3) + (R2/R4) – VOS3(R2/R3)] VOS3 VOSN – VOS2 × [R4/(R2 + R4)] + VOS2[R2/(R2 + R4)] 3VOS2 VOS3 VOS1[1 + (R4/R1) + (R4/R2) + (R4/R3)] – VOS2(R4/R2) – VOS3(R4/R3) Table 1. Output DC Offsets, One 2nd Order Section |
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