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LTC694-3.3 Datasheet(PDF) 11 Page - Linear Technology |
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LTC694-3.3 Datasheet(HTML) 11 Page - Linear Technology |
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11 / 20 page  LTC694-3.3/LTC695-3.3 11 69453fb APPLICATIONS INFORMATION If battery connections are made through long wires, a 10Ω to 100Ω series resistor and a 0.1μF capacitor are recommended to prevent any overshoot beyond VCC due to the lead inductance (Figure 4). Table 1 shows the state of each pin during battery back-up. When the battery switchover section is not used, connect VBATT to GND and VOUT to VCC. Table 1. Input and Output Status in Battery Back-Up Mode SIGNAL STATUS VCC C2 monitors VCC for active switchover. VOUT VOUT is connected to VBATT through an internal PMOS switch. VBATT The supply current is 1μA maximum. BATT ON Logic high. The open-circuit output voltage is equal to VOUT. PFI Power failure input is ignored. PFO Logic low. RESET Logic low. RESET Logic high. The open-circuit output voltage is equal to VOUT. LOW _ LINE Logic low. WDI Watchdog input is ignored. WDO Logic high. The open-circuit output voltage is equal to VOUT. CE IN Chip _ Enable input is ignored. CE OUT Logic high. The open-circuit output voltage is equal to VOUT. OSC IN OSC IN is ignored. OSC SEL OSC SEL is ignored. Memory Protection The LTC695-3.3 includes memory protection circuitry which ensures the integrity of the data in memory by pre- venting write operations when VCC is at invalid level. Two additional pins, CE IN and CE OUT, control the Chip _ Enable or Write inputs of CMOS RAM. When VCC is 3.3V, CE OUT follows CE IN with a typical propagation delay of 30ns. When VCC falls below the reset voltage threshold or VBATT, CE OUT is forced high, independent of CE IN. CE OUT is an alternative signal to drive the CE, CS, or Write input of battery backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 5 shows the timing diagram of CE IN and CE OUT. Figure 4. 10Ω/0.1μF Combination Eliminates Inductive Overshoot and Prevents Spurious Resets During Battery Replacement. The 2.7M Pulls the VBATT Pin to Ground While the Battery is Removed, Eliminating Spurious Resets 2.7M 0.1μF VBATT LTC694-3.3 LTC695-3.3 GND 694/5-3.3 F04 10Ω VCC V1 CE IN VOUT = VBATT CE OUT VOUT = VBATT V2 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS 694/5-3.3 F05 Figure 5. Timing Diagram for CE IN and CE OUT |
Similar Part No. - LTC694-3.3_15 |
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Similar Description - LTC694-3.3_15 |
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