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UPD754264GS Datasheet(PDF) 5 Page - NEC |
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UPD754264GS Datasheet(HTML) 5 Page - NEC |
5 / 68 page 5 µPD754264 1. PIN CONFIGURATION (TOP VIEW) • 20-pin Plastic SOP (300 mil, 1.27-mm pitch) µPD754264GS-×××-BA5 IC: Internally Connected (Connect to VDD directly) Pin Identification AN0, AN1 : Analog input 0,1 P70 to P73 : Port 7 AVREF : Analog reference P80 : Port 8 IC : Internally connected PTO0 to PTO2 : Programmable timer outputs 0 to 2 INT0 : External vectored interrupt 0 RESET : Reset KR4 to KR7 : Key returns 4 to 7 VDD : Positive power supply KRREN : Key return reset enable VSS : Ground P30 to P33 : Port 3 X1 and X2 : System clock (crystal/ceramic) P60 to P63 : Port 6 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RESET X1 X2 VSS IC VDD P60/AVREF P61/INT0 P62/AN0 P63/AN1 KRREN P80 P30/PTO0 P31/PTO1 P32/PTO2 P33 P70/KR4 P71/KR5 P72/KR6 P73/KR7 |
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