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LT1793 Datasheet(PDF) 7 Page - Linear Technology |
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LT1793 Datasheet(HTML) 7 Page - Linear Technology |
7 / 12 page 7 LT1793 CC HARA TERISTICS A TYPICALPERFOR CE Short-Circuit Output Current vs Temperature TEMPERATURE ( °C) –75 10 15 20 25 30 –25 50 25 100 1793 G19 35 40 –50 0 75 125 SINK SOURCE VS = ±15V Supply Current vs Temperature TEMPERATURE ( °C) –75 3 4 –25 50 25 100 1793 G20 5 –50 0 75 125 VS = ±15V VS = ±5V S APPLICATI I FOR ATIO LT1793 vs the Competition With improved noise performance, the LT1793 in the PDIP directly replaces such JFET op amps as the OPA111 and the AD645. The combination of low current and voltage noise of the LT1793 allows it to surpass most dual and single JFET op amps. The LT1793 can replace many of the lowest noise bipolar amps that are used in amplify- ing low level signals from high impedance transducers. The best bipolar op amps (with higher current noise) will eventually lose out to the LT1793 when transducer im- pedance increases. Figure 1. Comparison of LT1793, OP215, and AD822 Input Bias Current vs Common Mode Range COMMON MODE RANGE (V) –15 –100 –60 –40 –20 0 20 40 –10 –5 05 1793 F01 10 60 80 100 –80 15 LT1793 AD822 CURRENT NOISE = √2qIB OP215 TEMPERATURE ( °C) 0 300p 100p 3n 1n 30n 10n 100 1793 G21 30p 10p 3p 1p 0.3p 25 50 75 125 VS = ±15V VCM = –10 TO 13V BIAS CURRENT OFFSET CURRENT Input Bias and Offset Currents vs Chip Temperature The extremely high input impedance (1013 Ω) assures that the input bias current is almost constant over the entire common mode range. Figure 1 shows how the LT1793 stands up to the competition. Unlike the competition, as the input voltage is swept across the entire common mode range the input bias current of the LT1793 hardly changes. As a result the current noise does not degrade. This makes the LT1793 the best choice in applications where an amplifier has to buffer signals from a high impedance transducer. Offset nulling will be compatible with these devices with the wiper of the potentiometer tied to the negative supply (Figure 2a). No appreciable change in offset voltage drift 2 3 1 5 ∆VOS = ±13mV 50k 15V – 15V 4 6 7 2 3 1 5 ∆VOS = ±1.3mV 50k 10k 10k 15V – 15V (b) (a) 1793 F02 4 6 7 Figure 2 |
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