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LT1683EG Datasheet(PDF) 7 Page - Linear Technology |
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LT1683EG Datasheet(HTML) 7 Page - Linear Technology |
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7 / 24 page  7 LT1683 1683f Gate Drive GATE A, GATE B (Pins 1, 19): These pins connect to the gates of the external N-channel MOSFETs. GATE A and GATE B turn on with alternate clock cycles. These drivers are capable of sinking and sourcing at least 300mA. The GCL pin sets the upper voltage of the gate drive. The gate pins will not be activated until VIN reaches a minimum voltage as defined by the GCL pin (gate undervoltage lockout). The gate drive outputs have current limit protection to safe guard against accidental shorts. If the gate drive voltage is greater than about 1V the opposite gate drive is inhibited thus preventing cross conduction. GCL (Pin 3): This pin sets the maximum gate voltage to the GATE A and GATE B pins to the MOSFET gate drives. This pin should be either tied to a Zener, a voltage source or VIN. If the pin is tied to a Zener or a voltage source, the maximum gate drive voltage will be approximately VGCL – 0.2V. If it is tied to VIN, the maximum gate voltage is approximately VIN – 1.6. Approximately 50 µA of current can be sourced from this pin if VGCL < VIN – 0.8V. This pin also controls undervoltage lockout of the gate drives. If the pin is tied to a Zener or voltage source, the gate drive will not be enabled until VIN > VGCL + 0.8V. If this pin is tied to VIN, then undervoltage lockout is disabled. There is an internal 19V Zener tied from this pin to ground to provide a fail-safe for maximum gate voltage. Slew Control CAP A, CAP B (Pins 2, 18): These pins are the feedback nodes for the external voltage slewing capacitors. Nor- mally a small 1pf to 5pf capacitor is connected from this pin to the drain of its respective MOSFET. The voltage slew rate is inversely proportional to this capacitance and proportional to the current that the part will sink and source on this pin. That current is inversely proportional to RVSL. RCSL (Pin 15): A resistor to ground sets the current slew rate for the external drive MOSFETs during switching. The minimum resistor value is 3.3k and the maximum value is 68k. The time to slew between on and off states of the MOSFET current will determine how the di/dt related harmonics are reduced. This time is proportional to RCSL and RS (the current sense resistor) and maximum current. Longer times produce a greater reduction of higher fre- quency harmonics. RVSL (Pin 16): A resistor to ground sets the voltage slew rate for the drains of the external drive MOSFETs. The minimum resistor value is 3.3k and the maximum value is 68k. The time to slew between on and off states on the MOSFET drain voltage will determine how harmonics are reduced from this source. This time is proportional to RVSL, CVA/B and the input voltage. Longer times produce more rolloff of harmonics. CVA/B is the equivalent capaci- tance from CAP A or B to the drain of the MOSFET. Switch Mode Control SS (Pin 3): The SS pin allows for ramping of the switch current threshold at startup. Normally a capacitor is placed on this pin to ground. An internal 9 µA current source will charge this capacitor up. The voltage on the VC pin cannot exceed the voltage on SS. Thus peak current will ramp up as the SS pin ramps up. During a short circuit fault the SS pin will be discharged to ground thus reinitializing soft- start. When SS is below the VC clamp voltage the VC pin will closely track the SS pin. This pin can be left open if not used. PI FU CTIO S |
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