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LT1640L Datasheet(PDF) 10 Page - Linear Technology |
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LT1640L Datasheet(HTML) 10 Page - Linear Technology |
10 / 12 page 10 LT1640L/LT1640H APPLICATIONS INFORMATION supply input. The UV and OV pins are internally connected to analog comparators with 20mV of hysteresis. When the UV pin falls below its threshold or the OV pin rises above its threshold, the GATE pin is immediately pulled low. The GATE pin will be held low until UV is high and OV is low. The undervoltage and overvoltage trip voltages can be programmed using a three resistor divider as shown in Figure 10a. With R4 = 562k, R5 = 9.09k and R6 = 10K, the undervoltage threshold is set to 37V and the overvoltage threshold is set to 71V. The resistor divider will also gain up the 20mV hysteresis at the UV pin and OV pin to 0.6V and 1.2V at the input respectively. More hysteresis can be added to the UV threshold by connecting resistor R3 between the UV pin and the GATE pin as shown in Figure 10b. The new threshold voltage when the input moves from low to high is: VV R R RR RR RR UV LH UVH , ••• • = ++ 2 3 13 12 23 where VUVH is typically 1.243V. The new threshold voltage when the input moves from high to low is: VV R R RR RR RR V R R UV HL UVL GATE , ••• • –• = ++ 2 3 13 12 23 1 3 where VUVL is typically 1.223V. The new hysteresis value will be: VV R R RR RR RR V R R HYS UVHY GATE = ++ + 2 3 13 12 23 1 3 ••• • • With R1 = 562k, R2 = 16.9k and R3 = 1.62M, VGATE = 135mV and VUVHY = 20mV, the undervoltage threshold will be 43V (from low to high) and 37.6V (from high to low). The hysteresis is 5.4V. A separate resistor divider should be used to set the overvoltage threshold given by: VV RR R OV OVH = + 45 5 With R4 = 506k, R5 = 8.87k and VOVH = 1.223V, the overvoltage threshold will be 71V. Figure 10a. Undervoltage and Overvoltage Sensing VEE VDD LT1640L LT1640H R4 R5 R6 4 1640 F10a OV GND 3 2 – 48V UV 8 VUV = 1.223 R4 + R5+ R6 R5 + R6 () VOV = 1.223 R4 + R5+ R6 R6 () PWRGD/PWRGD Output The PWRGD/PWRGD output can be used to directly en- able a power module when the input voltage to the module is within tolerance. The LT1640L has a PWRGD output for modules with an active low enable input, and the LT1640H has a PWRGD output for modules with an active high enable input. When the DRAIN voltage of the LT1640H is high with respect to VEE (Figure 11), the internal transistor Q3 is turned off and R7 and Q2 clamp the PWRGD pin one diode drop ( ≈0.7V) above the DRAIN pin. Transistor Q2 sinks the module’s pull-up current and the module turns off. When the DRAIN voltage drops below VPG, Q3 will turn on, shorting the bottom of R7 to VEE and turning Q2 off. The VEE VDD LT1640L /LT1640H SENSE C1 0.033 µF 24V Q1 IRF530 R6 10 Ω 5% R1 562k 1% R3 1.62M 1% R2 16.9k 1% R4 506k 1% R5 8.87k 1% R1 0.02 Ω 5% 4 2 3 UV = 37.6V UV = 43V GND – 48V UV OV 56 8 GATE 1640 F10b OV = 71V Figure 10b. Programmable Hysteresis for Undervoltage Detection |
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