LTC1407A-1_15 datasheet(9/26 Pages) LINER

Part #	LTC1407A-1

Description	Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown

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Manufacturer	LINER [Linear Technology]

Direct Link	http://www.linear.com

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LTC1407-1/LTC1407A-1

9

14071fb

TYPICAL PERFORMANCE CHARACTERISTICS

CH0+ (Pin 1): Noninverting Channel 0. CH0+ operates

fully differentially with respect to CH0–, with a –1.25V to

1.25V differential swing with respect to CH0– and a 0 to

VDD absolute input range.

CH0– (Pin 2):

Inverting Channel 0. CH0– operates fully

differentially with respect to CH0+, with a 1.25V to –1.25V

differential swing with respect to CH0+ and a 0 to VDD

absolute input range.

VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and

a solid analog ground plane with a 10μF ceramic capacitor

(or 10μF tantalum in parallel with 0.1μF ceramic). Can be

overdriven by an external reference voltage ≥ 2.55V and

≤VDD.

CH1+ (Pin 4):

Noninverting Channel 1. CH1+ operates

fully differentially with respect to CH1–, with a –1.25V to

1.25V differential swing with respect to CH1– and a 0 to

VDD absolute input range.

CH1– (Pin 5):

Inverting Channel 1. CH1– operates fully

differentially with respect to CH1+, with a 1.25V to –1.25V

differential swing with respect to CH1+ and a 0 to VDD

absolute input range.

GND (Pins 6, 11): Ground and Exposed Pad. This single

ground pin and the Exposed Pad must be tied directly to

the solid ground plane under the part. Keep in mind that

analog signal currents and digital output signal currents

ﬂow through these connections.

VDD (Pin 7): 3V Positive Supply. This single power pin

supplies 3V to the entire chip. Bypass to GND pin and

solid analog ground plane with a 10μF ceramic capacitor

(or 10μF tantalum) in parallel with 0.1μF ceramic. Keep in

mind that internal analog currents and digital output signal

currents ﬂow through this pin. Care should be taken to

place the 0.1μF bypass capacitor as close to Pins 6 and 7

as possible.

SDO (Pin 8): Three-State Serial Data Output. Each pair of

output data words represent the two analog input channels

at the start of the previous conversion. The output format

is 2’s complement.

SCK (Pin 9): External Clock Input. Advances the conver-

sion process and sequences the output data on the rising

edge. One or more pulses wake from sleep.

CONV (Pin 10): Convert Start. Holds the two analog input

signals and starts the conversion on the rising edge. Two

pulses with SCK in ﬁxed high or ﬁxed low state starts nap

mode. Four or more pulses with SCK in ﬁxed high or ﬁxed

low state starts sleep mode.

VDD = 3V, TA = 25°C (LTC1407-1/LTC1407A-1)

Reference Voltage vs VDD

Reference Voltage

vs Load Current

PIN FUNCTIONS

VDD (V)

2.4890

2.4894

2.4898

2.4902

2.4892

2.4896

2.4900

2.8

3.0

3.2

3.4

14071 G26

2.6

3.6

LOAD CURRENT (mA)

0.4

0.8

1.2

1.6

14071 G27

2.0

0.2

0

0.6

1.0

1.4

1.8

2.4890

2.4894

2.4898

2.4902

2.4892

2.4896

2.4900

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LTC1407A-1 Datasheet(PDF) 9 Page - Linear Technology

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