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LT1339CN Datasheet(PDF) 7 Page - Linear Technology |
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LT1339CN Datasheet(HTML) 7 Page - Linear Technology |
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7 / 20 page  7 LT1339 SYNC (Pin 1): Oscillator Synchronization Pin with TTL- Level Compatible Input. Input drives internal rising edge triggered one-shot; sync signal on/off times should be ≥1µs (10% to 90% DC at 100kHz). Does not contain internal pull-up. Connect to SGND if not used. 5VREF (Pin 2): 5V Output Reference. Allows connection of external loads up to 10mA DC. (Reference is not available in shutdown.) Typically bypassed with 1 µF capacitor to SGND. CT (Pin 3): Oscillator Timing Pin. Connect a capacitor (CCT) to ground and a pull-up resistor (RCT) to the 5VREF supply. Typical values are CT = 1000pF and 10k ≤ RCT ≤ 30k. SL/ADJ (Pin 4): Slope Compensation Adjustment. Allows increased slope compensation for certain high duty cycle applications. Resistive loading of the pin increases effective slope compensation. A resistor divider from the 5VREF pin can tailor the onset of addi- tional slope compensation to specific regions in each switch cycle. Pin can be floated or connected to 5VREF if no additional slope compensation is required. (See Applications Information section for slope compensa- tion details.) IAVG (Pin 5): Average Current Limit Integration. Fre- quency response characteristic is set using the 50k Ω output impedance and external capacitor to ground. Averaging roll-off typically set at 1 to 2 orders of magni- tude under switching frequency. (Typical capacitor value ~1000pF for fO = 100kHz.) Shorting this pin to SGND will disable the average current limit function. SS (Pin 6): Soft Start. Generates ramping threshold for regulator current limit during start-up and after UVLO event by sourcing about 8 µA into an external capacitor. VC (Pin 7): Error Amplifier Output. RC load creates dominant compensation in power supply regulation feed- back loop to provide optimum transient response. (See Applications Information section for compensation de- tails.) SGND (Pin 8): Small-Signal Ground. Connect to negative terminal of COUT. VFB (Pin 9): Error Amplifier Inverting Input. Used as voltage feedback input node for regulator loop. Pin sources about 0.5 µA DC bias current to protect from an open feedback path condition. PIN FUNCTIONS VREF (Pin 10): Bandgap Generated Voltage Reference Decoupling. Connect a capacitor to signal ground. (Typi- cal capacitor value ~0.1 µF.) SENSE + (Pin 11): Current Sense Amplifier Inverting Input. Connect to most positive (DC) terminal of current sense resistor. SENSE – (Pin 12): Current Sense Amplifier Noninverting Input. Connect to most negative (DC) terminal of current sense resistor. RUN/SHDN (Pin 13): Precision Referenced Shutdown. Can be used as logic level input for shutdown control or as an analog monitor for input supply undervoltage protection, etc. IC is enabled when RUN/SHDN pin rising edge exceeds 1.25V. About 25mV of hysteresis helps assure stable mode switching. All internal functions are disabled in shutdown mode. If this function is not desired, connect RUN/SHDN to 12VIN (typically through a 100k resistor). See Applications Information section. PHASE (Pin 14): Output Driver Phase Control. If Pin 14 is not connected (floating), the topside driver operates the main switch, with the bottom side driver operating the synchronous switch. Shorting Pin 14 to ground reverses the roles of the output drivers. PHASE is typi- cally shorted to ground for inverting and boost configu- rations. Positive buck configuration requires the PHASE pin to float. See Applications Information section. PGND (Pin 15): Power Ground. References the bottom side output switch and internal driver control circuits. Connect with low impedance trace to VIN decoupling capacitor negative (ground) terminal. BG (Pin 16): Bottom Side Output Driver. Connects to gate of bottom side external power FET. 12VIN (Pin 17): 12V Power Supply Input. Bypass with at least 1 µF to PGND. TS (Pin 18): Boost Output Driver Reference. Typically connects to source of topside external power FET and inductive switch node. TG (Pin 19): Topside (Boost) Output Driver. Connects to gate of topside external power FET. VBOOST (Pin 20): Topside Power Supply. Bootstrapped via 1 µF capacitor tied to switch node (Pin 18) and Schottky diode connected to the 12VIN supply. |
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