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LTC1863L Datasheet(PDF) 9 Page - Linear Technology |
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LTC1863L Datasheet(HTML) 9 Page - Linear Technology |
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9 / 16 page  LTC1863L/LTC1867L 9 1863l7lfd For more information www.linear.com/LTC1863L APPLICATIONS INFORMATION Overview The LTC1863L/LTC1867L are complete, low power, multiplexed ADCs. They consist of a 12-/16-bit, 175ksps capacitive successive approximation A/D converter, a pre- cision internal reference, a configurable 8-channel analog input multiplexer (MUX) and a serial port for data transfer. Conversions are started by a rising edge on the CS/CONV input. Once a conversion cycle has begun, it cannot be restarted.Betweenconversions,theADCsreceiveaninput word for channel selection and output the conversion re- sult, and the analog input is acquired in preparation for the next conversion. In the acquire phase, a minimum time of 2.01µs will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the conversion, the internal differential 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The input is sucessively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by a low power, differential comparator that rejects common mode noise. At the end of a conversion, the DAC output balances the analog input. The SAR content (a 12-/16-bit data word) that represents theanaloginputisloadedintothe12-/16-bitoutputlatches. Analog Input Multiplexer The analog input multiplexer is controlled by a 7-bit input data word. The input data word is defined as follows: SD OS S1 S0 COM UNI SLP SD = SINGLE/DIFFERENTIAL BIT OS = ODD/SIGN BIT S1 = ADDRESS SELECT BIT 1 S0 = ADDRESS SELECT BIT 0 COM = CH7/COM CONFIGURATION BIT UNI = UNIPOLAR/BIPOLAR BIT SLP = SLEEP MODE BIT Examples of Multiplexer Options CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM GND ( –) 8 Single-Ended + + + + + + + 4 Differential + (–) + CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM ( –) 7 Single-Ended to CH7/COM + + + + + + + + (–) + (–) + (–) – (+) – (+) – (+) – (+) GND ( –) Combinations of Differential and Single-Ended + + + + + + – – { { { { { { 1863L7L AI01 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM Tables 1 and 2 show the configurations when COM = 0, and COM = 1. Table 1. Channel Configuration (When COM = 0, CH7/COM Pin Is Used as CH7) SD OS S1 S0 COM Channel Configuration “+” “–” 0 0 0 0 0 CH0 CH1 0 0 0 1 0 CH2 CH3 0 0 1 0 0 CH4 CH5 0 0 1 1 0 CH6 CH7 0 1 0 0 0 CH1 CH0 0 1 0 1 0 CH3 CH2 0 1 1 0 0 CH5 CH4 0 1 1 1 0 CH7 CH6 1 0 0 0 0 CH0 GND 1 0 0 1 0 CH2 GND 1 0 1 0 0 CH4 GND 1 0 1 1 0 CH6 GND 1 1 0 0 0 CH1 GND 1 1 0 1 0 CH3 GND 1 1 1 0 0 CH5 GND 1 1 1 1 0 CH7 GND CH7/COM (UNUSED) CH7/COM ( –) 1st Conversion 2nd Conversion + – + – + – + + { { { { CH2 CH3 CH4 CH5 CH2 CH3 CH4 CH5 1863L7L AI02 Changing the MUX Assignment “On the Fly” |
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