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LT1122DM Datasheet(PDF) 4 Page - Linear Technology |
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LT1122DM Datasheet(HTML) 4 Page - Linear Technology |
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4 / 8 page  4 LT1122 VS = ± 15V, VCM = 0V, – 40°C ≤ TA ≤ 85°C, unless otherwise noted. (Note 5) Settling Time Test Fixture ELECTRICAL C C HARA TERISTICS LT1122CC/DC LT1122AC/BC LT1122CS/DS SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS VOS Input Offset Voltage • 450 1900 500 2700 µV Average Temperature Coefficient • 620 7 28 µV/°C of Input Offset Voltage IOS Input Offset Current • 30 600 40 900 pA IB Input Bias Current • 230 2000 260 2700 pA AVOL Large Signal Voltage Gain VOUT = ± 10V, RL ≥ 2kΩ • 95 340 80 300 V/mV CMRR Common Mode Rejection Ratio VCM = ± 10V • 80 98 76 96 dB PSRR Power Supply Rejection Ratio VS = ± 10V to ± 17V • 83 100 78 98 dB Input Voltage Range • ±10 ±10.6 ± 10 ± 10.6 V VOUT Output Voltage Swing RL = 2kΩ • ±11.3 ±12.2 ± 11.3 ± 12.2 V SR Slew Rate AV = – 1 • 45 65 35 60 V/ µs 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 +15V 1 F TANT µ 0.1 F µ 1 F TANT µ 0.1 F µ TYPICAL SUPPLY BYPASSING FOR EACH AMP/BUFFER –10V (REGULATED) 1 2 TTL IN 4 5 74LS00 GROUND ALL OTHER INPUTS +10V (REGULATED) 6 3 SETTLING TIME OUTPUT (20 TIMES SUM NODE OUTPUT) 1k NO CONNECTION ON PINS 10, 11, 12, 14, AND 15 1N5712 +15V –15V 1.5k LT1223 51 – + 3 2 4 7 6 8 1 7 2 5 4 51 1N5712 SUMMING NODE OUTPUT –15V +15V *THIS RESISTOR CAN BE ADJUSTED TO NULL OUT ALL OFFSETS AT THE SETTLING TIME OUTPUT. THE AUTOMATED TESTER USES A SEPARATE AUTOZERO CIRCUIT. –15V (MEASURE INPUT PULSE HERE) VIN 5.1k 1% 4 –15V 3 2 7 6 LT1122 + – 2k 1% +15V 2k 1% DEVICE UNDER TEST 5pF +15V 7 1 5 2 8 51 51 HA5002 79 5.1k* 1% HA5002 4 LTC201A LT1122•TA02 + + –15V |
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