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PALCE16V8Z-25PC Datasheet(PDF) 7 Page - Lattice Semiconductor |
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PALCE16V8Z-25PC Datasheet(HTML) 7 Page - Lattice Semiconductor |
7 / 32 page PALCE16V8 and PALCE16V8Z Families 7 Power-Up Reset All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE16V8 will depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of the logic. Register Preload The register on the PALCE16V8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Security Bit A security bit is provided on the PALCE16V8 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback and verification of the programmed pattern by a device programmer, securing proprietary designs from competitors. The bit can only be erased in conjunction with the array during an erase cycle. Electronic Signature Word An electronic signature word is provided in the PALCE16V8 device. It consists of 64 bits of programmable memory that can contain user-defined data. The signature data is always available to the user independent of the security bit. Programming and Erasing The PALCE16V8 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its unprogrammed state. Erasure is automatically performed by the programming hardware. No special erase operation is required. Quality and Testability The PALCE16V8 offers a very high level of built-in quality. The erasability of the device provides a direct means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry. Technology The high-speed PALCE16V8 is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching. PCI Compliance PALCE16V8 devices in the -5/-7/-10 speed grades are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The PALCE16V8’s predictable timing ensures compliance with the PCI AC specifications independent of the design. Zero-Standby Power Mode The PALCE16V8Z features a zero-standby power mode. When none of the inputs switch for an extended period (typically 50 ns), the PALCE16V8Z will go into standby mode, shutting down |
Similar Part No. - PALCE16V8Z-25PC |
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