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GAL16V8D Datasheet(PDF) 15 Page - Lattice Semiconductor |
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GAL16V8D Datasheet(HTML) 15 Page - Lattice Semiconductor |
15 / 22 page Specifications GAL16V8 15 *C L includes test fixture and probe capacitance. Electronic Signature An electronic signature is provided in every GAL16V8 device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calcula- tions. Changing the electronic signature will alter the checksum. Security Cell A security cell is provided in the GAL16V8 devices to prevent un- authorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is pro- grammed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Latch-Up Protection GAL16V8 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots. Ad- ditionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots. Device Programming GAL devices are programmed using a Lattice Semiconductor- approved Logic Programmer, available from a number of manu- facturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. 1. 0 2 . 0 3. 0 4 . 0 5. 0 -6 0 0 -2 0 -4 0 0 Input V o lt ag e ( V olt s) TEST POINT Z0 = 50 Ω, CL = 35pF* FROM OUTPUT (O/Q) UNDER TEST +1.45V R1 GAL16V8D-3 Output Load Conditions (see figure at right) Test Condition R1 CL A50 Ω 35pF B High Z to Active High at 1.9V 50 Ω 35pF High Z to Active Low at 1.0V 50 Ω 35pF C Active High to High Z at 1.9V 50 Ω 35pF Active Low to High Z at 1.0V 50 Ω 35pF Switching Test Conditions (Continued) Output Register Preload When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. GAL16V8 devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing text vectors perform output register preload automatically. Input Buffers GAL16V8 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The GAL16V8 input and I/O pins have built-in active pull-ups. As a result, unused inputs and I/O's will float to a TTL "high" (logical "1"). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, VCC, or Ground. Doing this will tend to improve noise immunity and re- duce ICC for the device. Typical Input Pull-up Characteristic |
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