MACH210-20JC datasheet(11/47 Pages) LATTICE

Part #	MACH210-20JC

Description	High-Density EE CMOS Programmable Logic

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Manufacturer	LATTICE [Lattice Semiconductor]

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11

MACH210A-7 (Com’l)

CAPACITANCE (Note 1)

Parameter

Symbol

Parameter Description

Test Conditions

Typ

Unit

CIN

Input Capacitance

VIN = 2.0 V

VCC = 5.0 V, TA = 25

°C,

6

pF

COUT

Output Capacitance

VOUT = 2.0 V

f = 1 MHz

8

pF

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges

Parameter

Symbol

Parameter Description

Min

Max

Unit

tPD

Input, I/O, or Feedback to Combinatorial Output

7.5

ns

tS

Setup Time from Input, I/O or Feedback to Clock

D-Type

5.5

ns

T-Type

6.5

ns

tH

Register Data Hold Time

0

ns

tCO

Clock to Output

5ns

tWL

Clock Width

LOW

3

ns

tWH

HIGH

3

ns

D-Type

100

MHz

T-Type

91

MHz

fMAX

D-Type

133

MHz

T-Type

125

MHz

166.7

MHz

tSL

Setup Time from Input, I/O, or Feedback to Gate

5.5

ns

tHL

Latch Data Hold Time

0

ns

tGO

Gate to Output

6ns

tGWL

Gate Width LOW

3

ns

tPDL

Input, I/O, or Feedback to Output Through

9.5

ns

Transparent Input or Output Latch

tSIR

Input Register Setup Time

2

ns

tHIR

Input Register Hold Time

2

ns

tICO

Input Register Clock to Combinatorial Output

11

ns

tICS

Input Register Clock to Output Register Setup

D-Type

9

ns

T-Type

10

ns

tWICL

Input Register Clock Width

LOW

3

ns

tWICH

HIGH

3

ns

fMAXIR

Maximum Input Register Frequency

166.7

MHz

tSIL

Input Latch Setup Time

2

ns

tHIL

Input Latch Hold Time

2

ns

tIGO

Input Latch Gate to Combinatorial Output

12

ns

tIGOL

Input Latch Gate to Output Through Transparent Output Latch

14

ns

tSLL

Setup Time from Input, I/O, or Feedback Through

7.5

ns

Transparent Input Latch to Output Latch Gate

Maximum

Frequency

External Feedback

Internal Feedback (fCNT)

No Feedback

-7

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MACH210-20JC Datasheet(PDF) 11 Page - Lattice Semiconductor

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