Electronic Components Datasheet Search |
|
GAL16V8ZD-12QP Datasheet(PDF) 3 Page - Lattice Semiconductor |
|
GAL16V8ZD-12QP Datasheet(HTML) 3 Page - Lattice Semiconductor |
3 / 19 page Specifications GAL16V8Z GAL16V8ZD 3 The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accom- plished by development software/hardware and is completely trans- parent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes is illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the in- put/output configuration. These two global and 16 individual archi- tecture bits define all possible configurations in a GAL16V8Z/ZD. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will trans- parently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. Software compilers support the three different global OLMC modes as different device types. Most compilers also have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combina- torial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. For further details, refer to the compiler soft- ware manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively. These pins cannot be con- figured as dedicated inputs in the registered mode. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output. When using the standard GAL16V8 JEDEC fuse pattern generated by the logic compilers for the GAL16V8ZD, special attention must be given to pin 4 (DPP) to make sure that it is not used as one of the functional inputs. Output Logic Macrocell (OLMC) Compiler Support for OLMC |
Similar Part No. - GAL16V8ZD-12QP |
|
Similar Description - GAL16V8ZD-12QP |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |