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ISPLSI2128VE Datasheet(PDF) 6 Page - Lattice Semiconductor |
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ISPLSI2128VE Datasheet(HTML) 6 Page - Lattice Semiconductor |
6 / 19 page Specifications ispLSI 2128VE 6 External Timing Parameters Over Recommended Operating Conditions tpd1 UNITS TEST COND. 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Table 2-0030B/2128VE v.1.0 1 3 2 1 tsu2 + tco1 ( ) DESCRIPTION # PARAMETER A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd2 A 2 Data Propagation Delay ns fmax A 3 Clock Frequency with Internal Feedback MHz fmax (Ext.) — 4 Clock Frequency with External Feedback MHz fmax (Tog.) — 5 Clock Frequency, Max. Toggle MHz tsu1 — 6 GLB Reg. Setup Time before Clock, 4 PT Bypass ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass ns th1 — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu2 — 9 GLB Reg. Setup Time before Clock ns tco2 A 10 GLB Reg. Clock to Output Delay ns th2 — 11 GLB Reg. Hold Time after Clock ns tr1 A 12 Ext. Reset Pin to Output Delay, ORP Bypass ns trw1 — 13 Ext. Reset Pulse Duration ns tptoeen B 14 Input to Output Enable ns tptoedis C 15 Input to Output Disable ns tgoeen B 16 Global OE Output Enable ns tgoedis C 17 Global OE Output Disable ns twh — 18 External Synchronous Clock Pulse Duration, High ns twl — 19 External Synchronous Clock Pulse Duration, Low ns -135 MIN. -100 MIN. MAX. MAX. — 7.5 — 10.0 —— 135 — 100 — —— —— —— —— 0.0 — 6.0 — —— 0.0 — —— 5.0 — —— —— —— —— 3.5 —— 3.5 —— 100 143 5.0 4.0 — — 5.0 — 9.0 — 12.0 12.0 7.0 7.0 10.0 77 100 6.5 0.0 8.0 0.0 6.5 5.0 5.0 13.0 5.0 6.0 12.5 15.0 15.0 9.0 9.0 |
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