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ISPLSI5512VA-100LB388 Datasheet(PDF) 7 Page - Lattice Semiconductor |
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ISPLSI5512VA-100LB388 Datasheet(HTML) 7 Page - Lattice Semiconductor |
7 / 26 page Specifications ispLSI 5512VA 7 Global Clock Distribution The ispLSI 5000V Family has four dedicated clock input pins: CLK0 - CLK3. CLK0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest internal clock speed. The clock inversion is available on the remaining CLK1 - CLK3 signals. By sharing the pins with the I/O pins, CLK2 and CLK3 can not only be inverted but also is available for logic implementation through GRP signal routing. Figure 5 shows these different clock distribution options. Figure 5. ispLSI 5000V Global Clock Structure CLK0 CLK1 CLK 0 CLK 1 IO/CLK 2 IO/CLK 3 CLK2 CLK3 To GRP To GRP SET/RESET GSET/GRST |
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