6

Specifications ispLSI 2064VE

External Timing Parameters

Over Recommended Operating Conditions

UNITS

-100

MIN.

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

Table 2-0030B/2064VE

1

3

2

1

tsu2 + tco1

(

)

MAX.

DESCRIPTION

#

PARAMETER

A

1

Data Propagation Delay, 4PT Bypass, ORP Bypass

—

10.0

ns

A

2

Data Propagation Delay

—

ns

A

3

Clock Frequency with Internal Feedback

100

—

MHz

—

4

Clock Frequency with External Feedback

—

MHz

—

5

Clock Frequency, Max. Toggle

—

MHz

—

6

GLB Reg. Setup Time before Clock, 4 PT Bypass

—

ns

A

7

GLB Reg. Clock to Output Delay, ORP Bypass

—

ns

—

8

GLB Reg. Hold Time after Clock, 4 PT Bypass

0.0

ns

—

9

GLB Reg. Setup Time before Clock

8.0

ns

A

10

GLB Reg. Clock to Output Delay

—

ns

—

11

GLB Reg. Hold Time after Clock

0.0

ns

A

12

Ext. Reset Pin to Output Delay

—

ns

—

13

Ext. Reset Pulse Duration

6.5

ns

B

14

Input to Output Enable

—

ns

C

15

Input to Output Disable

—

ns

B

16

Global OE Output Enable

—

ns

C

17

Global OE Output Disable

—

ns

—

18

External Synchronous Clock Pulse Duration, High

5.0

—

ns

—

19

External Synchronous Clock Pulse Duration, Low

5.0

—

ns

77

100

6.5

5.0

—

—

6.0

—

13.5

—

15.0

15.0

9.0

9.0

13.0

-135

MIN. MAX.

—

7.5

—

135

—

—

—

—

—

0.0

6.0

—

0.0

—

5.0

—

—

—

—

3.5

—

3.5

—

100

143

5.0

4.0

—

—

5.0

—

10.0

—

12.0

12.0

7.0

7.0

10.0