3.3V In-System Programmable

SuperBIG™ High Density PLD

81080v_03

1

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Features

• SuperBIG HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 3.3V Power Supply

— 60,000 PLD Gates/1080 Macrocells

— 192-360 I/O Pins Supporting 3.3V/2.5V I/O

— 1440 Registers

— High-Speed Global and Big Fast Megablock (BFM)

Interconnect

— Wide 20-Macrocell Generic Logic Block (GLB) for

High Performance

— Wide Input Gating (44 Inputs per GLB) for Fast

Counters, State Machines, Address Decoders, Etc.

— PCB-Efficient Ball Grid Array (BGA) Package

Options

—

—

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path

Optimization

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

3.3V IN-SYSTEM PROGRAMMABLE

• ARCHITECTURE FEATURES

— Enhanced Pin-Locking Architecture, Symmetrical

Generic Logic Blocks Connected by Hierarchical

Big Fast Megablock and Global Routing Planes

— Product Term Sharing Array Supports up to 28

Product Terms per Macrocell Output

— Macrocells Support Concurrent Combinatorial and

Registered Functions

— Embedded Tristate Bus Can Be Used as an Internal

Tristate Bus or as an Extension of an External

Tristate Bus

— Macrocell and I/O Registers Feature Multiple Control

Options, Including Set, Reset and Clock Enable

— I/O Pins Support Programmable Bus Hold, Pull-Up,

Open-Drain and Slew Rate Options

— Separate VCCIO Power Supply to Support 3.3V or

2.5V Input/Output Logic Levels

— I/O Cell Register Programmable as Input Register for

Fast Setup Time or Output Register for Fast Clock to

Output Time

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

ispLSI 8000V Family Description

The ispLSI 8000V Family of Register-Intensive, 3.3V

SuperBIG In-System Programmable Logic Devices is

based on Big Fast Megablocks of 120 registered macro-

cells and a Global Routing Plane (GRP) structure

Global Routing Plane

12

I/O

12

I/O

Big Fast Megablock 0

12

I/O

12

I/O

Big Fast Megablock 1

12

I/O

12

I/O

Big Fast Megablock 3

12

I/O

12

I/O

Big Fast Megablock 4

12

I/O

12

I/O

Big Fast Megablock 6

12

I/O

12

I/O

Big Fast Megablock 5

12

I/O

12

I/O

Big Fast Megablock 7

12

I/O

12

I/O

Big Fast Megablock 8

12

I/O

12

I/O

Big Fast Megablock 2

12

I/O

12

I/O

12

I/O

12

I/O

12

I/O

12

I/O

12

I/O

12

I/O

12

I/O

12

I/O

12

I/O

12

I/O

Boundary

Scan

81080v block

July 2000