Specifications ispLSI 2192VE

5

External Timing Parameters

Over Recommended Operating Conditions

UNITS

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

Table 2-0030A/2192VE

1

3

2

1

tsu2 + tco1

(

)

DESCRIPTION

#

PARAMETER

A

1

Data Propagation Delay, 4PT Bypass, ORP Bypass

ns

A

2

Data Propagation Delay

ns

A

3

Clock Frequency with Internal Feedback

MHz

–

4

Clock Frequency with External Feedback

MHz

–

5

Clock Frequency, Max. Toggle

MHz

–

6

GLB Reg. Setup Time before Clock, 4 PT Bypass

ns

A

7

GLB Reg. Clock to Output Delay, ORP Bypass

ns

–

8

GLB Reg. Hold Time after Clock, 4 PT Bypass

ns

–

9

GLB Reg. Setup Time before Clock

ns

A

10

GLB Reg. Clock to Output Delay

ns

–

11

GLB Reg. Hold Time after Clock

ns

A

12

Ext. Reset Pin to Output Delay

ns

–

13

Ext. Reset Pulse Duration

ns

B

14

Input to Output Enable

ns

C

15

Input to Output Disable

ns

B

16

Global OE Output Enable

ns

C

17

Global OE Output Disable

ns

–

18

External Synchronous Clock Pulse Duration, High

ns

–

19

External Synchronous Clock Pulse Duration, Low

ns

-180

MIN. MAX.

–

5.0

–

180

–

–

–

–

–

0.0

4.5

–

0.0

–

4.0

–

–

–

–

2.5

–

2.5

–

125

200

3.5

3.5

–

–

4.5

–

7.0

–

10.0

10.0

5.0

5.0

7.5

-225

MIN. MAX.

–

4.0

–

225

–

–

–

–

–

0.0

3.5

–

0.0

–

3.5

–

–

–

–

2.0

–

2.0

–

150

250

2.5

3.2

–

–

3.7

–

6.0

–

6.0

6.0

4.5

4.5

6.2