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ISPLSI2128VE-180LT176 Datasheet(PDF) 9 Page - Lattice Semiconductor |
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ISPLSI2128VE-180LT176 Datasheet(HTML) 9 Page - Lattice Semiconductor |
9 / 19 page Specifications ispLSI 2128VE 9 ispLSI 2128VE Timing Model GLB Reg Delay I/O Pin (Output) ORP Delay Feedback Reg 4 PT Bypass 20 PT XOR Delays Control PTs I/O Pin (Input) Y0,1,2 GRP GLB Reg Bypass ORP Bypass DQ RST RE OE CK I/O Delay I/O Cell ORP GLB GRP I/O Cell #24 #25, 26, 27 #33, 34, 35 #43, 44 #36 Reset Ded. In #21 #20 #28 #29, 30, 31, 32 #38, 39 GOE 0 #42 #40, 41 0491/2032 #22 Comb 4 PT Bypass #23 #37 #45 Derivations of tsu, th and tco from the Product Term Clock = = = = tsu 2.8ns Logic + Reg su - Clock (min) ( tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8) = = = = th Clock (max) + Reg h - Logic ( tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8) = = = = tco Note: Calculations are based upon timing specifications for the ispLSI 2128VE-250L. Clock (max) + Reg co + Output ( tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4) Table 2-0042/2128VE v.1.0 2.5ns 7.0ns |
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