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UM1546 Datasheet(PDF) 9 Page - STMicroelectronics |
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UM1546 Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 17 page UM1546 System overview Doc ID 023229 Rev 1 9/17 Figure 6. RC5 frame reception mechanism The decoding algorithm uses a small finite state machine as follows: ● State 1: Enable EXT interrupt and start timer with ARR value for 3.5 ms overflow time. Go to State 2 when timer overflow occurs. ● State 2: Wait for first EXT interrupt, when it occurs, initialize and start timer and go to State 3. ● State 3: Wait for second EXT interrupt. When it occurs, stop timer and validate ½ bit time period. If valid, use it to calculate ¾ bit time and go to State 4, or else reset state to State 1. ● State 4: Wait for EXT interrupt. When it occurs (red downward arrow), disable EXT interrupt and start timer with ARR set to ¾ bit time. Go to State 5. ● State 5: When timer overflow interrupt occurs, sample the data line (green upward arrow) and push its value into the RC5 data sampling variable. If all 13 bits are sampled (including the last idle state), give the valid decoded output and go back to State 1 for the next detection cycle, or else re-enable EXT interrupt and go to State 4. The algorithm synchronizes the first half midpoint sampling location (green upward arrow) of each bit with the logic transition point of the previous bit (red downward arrow). The field bit is not decoded in the existing algorithm but this can be easily incorporated with minor modifications in the firmware. 2.2 Hardware layout The STEVAL-IHM037V1 component layout for top and bottom layers is shown below in Figure 6 and 7 respectively. It helps the user to locate different components / sections on the board. AM12345v1 S F C 01100011001 RC5 frame to be transmitted IR remote control output (IR LED) EXT Interrupt Data line sampling ¾ bit time delay from EXT interrupt Decoded output of IR receiver module ½ bit time |
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