UPD72850A datasheet(8/48 Pages) NEC

Part #	UPD72850A

Description	IEEE1394 400Mbps PHY

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Manufacturer	NEC [NEC]

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Data Sheet S14452EJ1V0DS00

8

µµµµPD72850A

1.2 Link Interface Pins

Name

Pin No.

I/O

Function

D0

15

I/O

Data input/output (bit 0)

D1

16

I/O

Data input/output (bit 1)

D2

18

I/O

Data input/output (bit 2)

D3

19

I/O

Data input/output (bit 3)

D4

21

I/O

Data input/output (bit 4)

D5

22

I/O

Data input/output (bit 5)

D6

24

I/O

Data input/output (bit 6)

D7

25

I/O

Data input/output (bit 7)

CTL0

12

I/O

Link interface control (bit 0)

CTL1

13

I/O

Llink interface control (bit 1)

LREQ

6

I

Link request input

SCLK

9

O

Link control output clock

LPS 1: 49.152 MHz output

LPS 0: Clamp to 0 (The clock signal will be output within 25

µsec after change

to “0”)

LPS

5

I

Link power status input

0: Link power off

1: Link power on (PHY/Link direct connection)

Clock signal of about 300 kHz (if isolation)

LKON

78

O

Link-on signal output pin

Link-on signal is 6.144 MHz clock output.

Please refer to 4.2 Link-on Indication.

Direct

77

I

PHY/Link isolation barrier control input

0: Isolation barrier

1: PHY/Link direct connection

1.3 Control Pins

Name

Pin No.

I/O

Function

PC0

2

I

PC1

1

I

PC2

79

I

Power class set input

This pin status will be loaded to Pwr_class bit which allocated to PHY register 4H.

IEEE1394-1995 chapter [4.3.4.1]

CMC

3

I

Configuration manager capable setting.

This pin status will be loaded to Contender bit which allocated to PHY register 4H.

0: Non contender

1: Contender

RESETB

30

I

Power on reset input.

Connect to DGND through a 0.1

µF capacitor.

0: Reset

1: Normal

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