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UPD72001L-11 Datasheet(PDF) 8 Page - NEC |
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UPD72001L-11 Datasheet(HTML) 8 Page - NEC |
8 / 40 page µPD72001-11, 72001-A8 8 Table 1-1. Pin Status at Reset Pin Name I/O Pin Status RESET (system reset) Channel reset WR I – – RD I – – B/A I – – C/D I – – D7 to D0 I/O – – INT O High impedance High impedance INTAK I – – PRI I – – PRO O Depends on PRI Depends on PRI DRQTXA O “L” “L” DRQRXA O “L” “L” DTRA/DRQTXB, O DTR function, “H” Retains current status DTRB/DRQRXB TXDA, TXDB O “H” “H” RXDA, RXDB I – – TRXCA, TRXCB I/O Input status Retains current status XI1A/STRXCA I – – XI1B/STRXCB XI2A/SYNCA I/O Input status Retains current status XI2B/SYNCB RTSA, RTSB O “H” “H” CTSA, CTSB I – – DCDA, DCDB I – – – : Undefined (4) CLK (System Clock) ... Input This pin inputs the system clock. The input frequency must be five times that of the data transfer rate or higher. (5) WR (Write) ... Input This pin inputs a write control signal for control words and transmit data. This pin is active-low. (6) RD (Read) ... Input This pin inputs a read control signal for status and receive data. This pin is active-low. (7) B/A (Channel B/Channel A) ... Input This pin inputs a signal to select a channel to be accessed when data is written or read. When this pin is “L”, channel A is selected; when it is “H”, channel B is selected. (8) C/D (Control/Data) ... Input This pin inputs a signal that determines the type of the data on the data bus when the data is written or read. |
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