UPD72107CW datasheet(11/32 Pages) NEC

Part #	UPD72107CW

Description	LAP-B CONTROLLER(Link Access Procedure Balanced mode)

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Manufacturer	NEC [NEC]

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11

µPD72107

SDIP

QFP

QFJ

Active

Pin No.

Level

RxD

3

14

4

I

–

A serial receive data input pin.

(Receive Data)

RxC

2

13

3

I

–

When CLK is set to 01 or 10 by “operation mode

(Receive Clock)

setting LCW”

Sixteen times the clock input of the transmit/receive

clock for the on-chip DPLL of the

µPD72107

When CLK is set to 00 by “operation mode setting

LCW”

One time the clock input of the receive clock

Remark LCW: abbreviation for Link Command Word

1.2 Pin Status after Reset of

µPD72107

The status of the output pins and input/output pins after reset in the

µPD72107 is as shown in Table 1-1.

Table 1-1. Pin Status after Reset

Pin Number

64-pin SDIP

80-pin QFP

68-pin QFJ

4

16

6

TxC

I/ONote

High impedance

5

17

7

TxD

O

H

15, 16

30, 31

17, 18

A0, A1

I/ONote

High impedance

17 to 30

32 to 47

19 to 32

A2 to A15

ONote

High impedance

(except 40, 41)

31 to 38

48 to 58

33 to 41

A16D8 to A23D15

I/ONote

High impedance

(except 50, 51, 55)

(except 35)

39 to 46

59 to 67

42 to 49

D0 to D7

I/ONote

High impedance

(except 61)

52

75

56

MRD

ONote

High impedance

53

76

57

MWR

ONote

High impedance

54

77

58

UBE

I/ONote

High impedance

55

78

59

INT

O

L

57

2

61

HLDRQ

O

L

60

5

64

ASTB

O

L

61

6

65

AEN

O

L

64

10

68

RTS

O

H

Note 3-state

Remarks 1. The status after reset is released is the same as the status during reset.

2. Input low level to the RESET pin for more than 7 clocks of the system clock.

I/O

Pin Name

Function

Pin Name

During Reset

I/O

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