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LTC3422 Datasheet(PDF) 11 Page - Linear Technology |
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LTC3422 Datasheet(HTML) 11 Page - Linear Technology |
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11 / 16 page  LTC3422 11 3422fa OPERATIO APPLICATIO S I FOR ATIO the input source. It also allows for inrush current limiting at turn-on, minimizing surge currents seen by the input supply. Note that to obtain the advantages of output disconnect, there must not be any external Schottky diodes connected between the SW pin and VOUT. Note: Board layout is extremely critical to minimize voltage overshoot on SW due to stray inductance. Keep the output filter capacitors as close as possible to VOUT and use very low ESR/ESL ceramic capacitors tied to a good ground plane. where: f = Operating Frequency in MHz Ripple = Allowable Inductor Current Ripple (Amps Peak-Peak) VIN(MIN) = Minimum Input Voltage VOUT(MAX) = Maximum Output Voltage The inductor current ripple is typically set 20% to 40% of the maximum inductor current. For high efficiency, choose an inductor with high fre- quency core material, such as ferrite, to reduce core losses. The inductor should have low ESR (equivalent series resistance) to reduce the I2R losses and must be able to handle the peak inductor current without saturat- ing. Molded chokes or chip inductors usually do not have enough core to support peak inductor currents in the 2A to 3A region. To minimize radiated noise, use a toroidal or shielded inductor. See Table 1 for suggested inductor suppliers and Table 2 for a list of capacitor suppliers. Table 1. Inductor Vendor Information SUPPLIER PHONE FAX WEB SITE Coilcraft (847) 639-6400 (847) 639-1469 www.coilcraft.com CoEv (800) 277-7040 (650) 361-2508 www.circuitprotection. Magnetics com/magnetics.asp Murata USA: USA: www.murata.com (814) 237-1431 (814) 238-0490 (800) 831-9172 Sumida USA: USA: www.sumida.com (847) 956-0666 (847) 956-0702 Japan: Japan: 81-3-3607-5111 81-3-3607-5144 TDK (847) 803-6100 (847) 803-6296 www.component.tdk.com TOKO (847) 297-0070 (847) 669-7864 www.toko.com Wurth (201) 785-8800 (201) 785-8810 www.we-online.com SW 1 VIN VIN 2 BURST 3 SS 4 SHDN MULTIPLE VIAS TO GROUND PLANE LTC3422 VOUT VOUT SYNC RT VC FB 3422 F01 5 10 9 8 7 6 Figure 1. Recommended Component Placement. Traces Carrying High Current are Direct (GND, SW, VIN, VOUT). Trace Area at FB and VC are Kept Low. Lead Length to Battery Should be Kept Short. VIN and VOUT Ceramic Capacitors Should be as Close to the LTC3422 Pins as Possible COMPONENT SELECTION Inductor Selection The high frequency operation of the LTC3422 allows the use of small surface mount inductors. The minimum inductance value is proportional to the operating fre- quency and is limited by the following constraints: L VV OUT MAX IN MIN > () 3 ƒƒ and L > V • Ripple • V IN(MIN) OUT(MAX) •– () ( ) It should also be noted that the LTC3422 provides inrush current limiting without reducing the maximum load cur- rent capability during start-up. The internally set peak current command of the LTC3422 is allowed to gradually increase during the soft-start period until it reaches the nominal maximum level. |
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Similar Description - LTC3422 |
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