Overview of 16-bit SDADC

AN4207

10/28

Doc ID 023945 Rev 1

Figure 5.

Input signal range in single ended zero reference mode

Note:

When channel p (with p is even) is used in differential mode, the channel p+1 is

automatically used as minus input (SDADCx_AINyM) and therefore channel p+1 can not be

used in single ended mode (zero reference mode or offset mode).

When channel 4 is configured in differential mode channel 5 is automatically used as minus

input and therefore channel 5 can not be used either in single ended offset mode or in single

ended zero reference mode.

2.1.3

SDADC voltage references

The SDADC reference voltage is selectable among four sources:

1.

VREFINT1: A 1.2V embedded reference voltage

2.

VREFINT2: A 1.8V embedded reference voltage

3.

VDDSD: The SDADC analog supply voltage. It ranges from 2.2 V to 3.6 V

4.

VREFSD+: The external SDADC reference voltage. It ranges from 1.1 V to VDDSD

The table below shows the voltage weights per bit (step size) using three possible

references.

SDADCx_AINyP

Vref/gain

MSv31131V1

Table 2.

Voltage step sizes

VREFSD+

µV/bit

VREINT1: 1.2

18.46

VREINT2: 1.8

27.69

3.3V

50.35