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PM0215 Datasheet(PDF) 9 Page - STMicroelectronics |
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PM0215 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 91 page  PM0215 About this document Doc ID 022979 Rev 1 9/91 1.3 About the STM32 Cortex-M0 processor and core peripherals The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: ● a simple architecture that is easy to learn and program ● ultra-low power, energy efficient operation ● excellent code density ● deterministic, high-performance interrupt handling ● upward compatibility with Cortex-M processor family. The Cortex-M0 processor is built on a highly area and power optimized 32-bit processor core, with a 3-stage pipeline von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. The Cortex-M0 processor implements the ARMv6-M architecture, which is based on the 16- bit Thumb® instruction set and includes Thumb-2 technology. This provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers. Figure 1. STM32 Cortex-M0 implementation The Cortex-M0 processor closely integrates a configurable nested vectored interrupt controller (NVIC), to deliver industry-leading interrupt performance. The NVIC: ● includes a non-maskable interrupt (NMI) ● provides zero jitter interrupt option ● provides four interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to abandon and restart load-multiple and store-multiple operations. Interrupt handlers do not require any assembler wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including a deep sleep function that enables the entire device to be rapidly powered down. &RUWH[0SURFHVVRU &RUWH[0 SURFHVVRU FRUH %XVPDWUL[ 1HVWHG 9HFWRUHG ,QWHUUXSW &RQWUROOHU 19,& ,QWHUUXSWV 'HEXJ $FFHVV3RUW '$3 $+%/LWHLQWHUIDFHWRV\VWHP 6HULDO:LUH 'HEXJ 'HEXJJHU LQWHUIDFH %UHDNSRLQW DQG ZDWFKSRLQW XQLW &RUWH[0FRPSRQHQWV 069 |
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