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LT3804 Datasheet(PDF) 8 Page - Linear Technology |
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LT3804 Datasheet(HTML) 8 Page - Linear Technology |
8 / 16 page LT3804 8 3804i Synchronization and Oscillator Frequency Setting The switching is synchronized to the secondary winding falling edge and the synchronization threshold is typically 2.5V. The synchronization falling edge triggers an internal inverted ramp (see Figure 2) and starts a new switching cycle for the leading edge voltage mode PWM. The reason for using leading edge modulation is to leave the trans- former primary side peak current sensing undisturbed. For proper synchronization, the oscillator frequency should be set lower than the system switching frequency with tolerances taken into account. fOSC < (fSL • 0.8) fSL is the low limit of the system switching frequency and 0.8 is the tolerance of fOSC. For example, given a system operating at 200kHz with 15% tolerance, then fSL = 200kHz • 85% = 170kHz; and fOSC < (170kHz • 0.8), so fOSC should be set below 136kHz. Once fOSC is determined, CSET can be calculated by CSET = (103540pF/fOSC(kHz)) – 18pF. For fOSC = 200kHz, CSET = 500pF. Output Voltage Programming The LT3804 uses true remote sensing (separate ground sensing pins, GNDS1 for the first output and GNDS2 for the second output) to eliminate output error pickup due to parasitic resistance. The feedback reference voltages VREF1 and VREF2 are 0.6V referred to GNDS1 and GNDS2 respectively. The output voltage can be easily programmed by a resistor divider, as shown in the Block Diagram: VOUT1 = 0.6 (1 + R13/R14) VOUT2 = 0.6 (1 + R3/R4) where R14 connects to GNDS1 and R4 connects to GNDS2. For accurate sensing results, GNDS1 and GNDS2 should stay within –0.1V and 0.1V referred to GND. Note that if either GNDS1 or GNDS2 is not connected, the LT3804 will be shut down. Power Good When both outputs reach between 90% and 110% of the programmed level, VPGOOD goes high( a pull-up resistor is required if the function is used) to signal power good. If either output rises above 110% or drops below 90%, VPGOOD goes low after a 200µs delay. PGIN1 senses the first output and PGIN2 senses the second output with a resistor divider. PGIN1 and PGIN2 are compared to the references VREF1 and VREF2 respectively. Resistor dividers should be connected to GNDS1 and GNDS2 with respect to each output. Current Limit CA1 The first output current limit is set by the 50mV threshold across CL1P and CL1N, the inputs of the amplifier CA1. By connecting an external resistor RS1(see Block Diagram), the current limit is set for 50mV/RS1. C17 on ILCOMP1 stablizes the current limit loop. If current limit is not used, both CL1P and CL1N should be grounded and C17 is not needed. Current Limit CA2 The second output current limit is set by the 50mV threshold across CL2P and CL2N, the inputs of the ampli- fier CA2. By connecting an external resistor RS2 (see Block Diagram), the current limit is set for 50mV/RS2. R6 and C6 on ILCOMP2 stablize the current limit loop. If current limit is not used, both CL2P and CL2N should be grounded and the BGS pin should also be grounded to disable compara- tor CA2; R6 and C6 are not needed. APPLICATIO S I FOR ATIO |
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