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UPD705102GM-133-8ED Datasheet(PDF) 11 Page - NEC |
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UPD705102GM-133-8ED Datasheet(HTML) 11 Page - NEC |
11 / 80 page µPD705102 11 Data Sheet U13675EJ2V1DS00 3. CPU FUNCTION The features of the CPU function are as follows: • High-performance 32-bit architecture for embedded control applications • Cache memory Instruction cache: 4 Kbytes Data cache: 4 Kbytes • Internal RAM Instruction RAM: 4 Kbytes Data RAM: 4 Kbytes • 1-clock pitch pipeline structure • 16-/32-bit length instruction format • Address/data separated type bus • 4-Gbyte linear address • Thirty-two 32-bit general registers • Register/flag hazard interlock is handled by hardware • 16 levels of interrupt response • 16-bit bus fixed function • 16-bit bus system can be constructed • Ideal instructions for any application field: • Sum-of-products operation • Saturation operation • Branch prediction • Concatenation shift • Block transfer instruction |
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