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LT1993-10 Datasheet(PDF) 10 Page - Linear Technology |
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LT1993-10 Datasheet(HTML) 10 Page - Linear Technology |
10 / 16 page LT1993-10 10 199310fb +OUTFILTERED, –OUTFILTERED (Pins 6, 7): Filtered Outputs. These pins add a series 25 Ω resistor from the unfiltered outputs and three 12pF capacitors. Each output has 12pF to VEE, plus an additional 12pF between each pin (See the Block Diagram). This filter has a –3dB bandwidth of 175MHz. ENABLE (Pin 11): This pin is a TTL logic input referenced to the VEEC pin. If low, the LT1993-10 is enabled and draws typically 100mA of supply current. If high, the LT1993-10 is disabled and draws typically 250µA. –INA, –INB (Pins 14, 13): Negative Inputs. These pins are normally tied together. These inputs may be DC- or AC- coupled. If the inputs are AC-coupled, they will self-bias to the voltage applied to the VOCM pin. +INA, +INB (Pins 16, 15): Positive Inputs. These pins are normally tied together. These inputs may be DC- or AC- coupled. If the inputs are AC-coupled, they will self-bias to the voltage applied to the VOCM pin. Exposed Pad (Pin 17): Tie the pad to VEEC (Pin 12). If split supplies are used, DO NOT tie the pad to ground. PI FU CTIO S BLOCK DIAGRA + – 14 –INA 5 +OUT 199310 BD 3 VCCA 10 VCCB 1 VCCC 11 ENABLE 13 –INB 12pF VCCA A VEEA VEEA 100 Ω 100 Ω 500 Ω 500 Ω 25 Ω 500 Ω 6 +OUTFILTERED – + 16 +INA 8 –OUT 15 +INB VCCB B VEEB VEEB 100 Ω 100 Ω 25 Ω 500 Ω 12pF 12pF 7 –OUTFILTERED 12 VEEC 9 VEEB 4 VEEA + – VEEC C VCCC 2 VOCM BIAS |
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