11

LTC3405A-1.375

3405a1375f

3405A1375 F05c

20µs/DIV

Burst Mode OPERATION

100mV/DIV

AC

COUPLED

200mA/DIV

200mA/DIV

LOAD CURRENT (mA)

100

90

80

70

60

50

40

30

20

10

0

0.1

10

100

1000

3405A1375 F05b

1

2.2µF

CER

2.7V

TO 4.2V

LTC3405A-1.375

RUN

MODE

3

10µH*

3405A1375 F05a

5

4

6

1

2

SW

GND

10µF

CER

1.375V

* MURATA LQHMCN10002

** MURATA 0603 GRM188R60G106ME47B

*** MURATA 0603 GRM188R61A225KE34B

APPLICATIO S I FOR ATIO

Figure 4. LTC3405A-1.375 Suggested Layout

LTC3405A-1.375

GND

3405A1518 F04

PIN 1

SW

L1

f = 1.5MHz in equation (3) gives:

L

V

MHz

mA

V

V

H

=

−

⎛

⎝

⎜

⎞

⎠

⎟ ≅

µ

1 375

15

60

1

1 375

42

10

.

.(

)

.

.

Figure 5a. Small Footprint Application

Figure 5c.

For best efficiency choose a 200mA or greater inductor

with less than 0.3Ω series resistance.

ESR of less than 0.5Ω. In most cases, a ceramic capacitor

will satisfy this requirement.

Figure 5 shows the complete circuit along with its effi-

ciency curve.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Figure 5b. LTC3405A-1.375 Small Footprint Efficiency