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PD16602 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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PD16602 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 18 page  9 µµµµPD16602 (4) Relatonship with HS and PL/NL HS PL/NL CLK SPR (SPL) tHS-SETUP tHS-HOLD tHS-SP Sampling period 01 2 0 1 2 26 27 Hi-Z Output period Caution HS and PL/NL edges have no relationship with clock timing. Timing Item Symbol Description Horizontal synchronization setup time tHS-SETUP Setup time of PL/NL signal with respect to HS. Secure 50 nsMIN. at least. Horizontal synchronization hold time tHS-HOLD PL/NL hold time. Secure 250 nsMIN. at least. The hold capacitance at this time is at common potential VCOM, but the output buffer does not reach VCOM, and therefore sampling is not possible. Sampling start time tHS-SP Time for the output buffer to reach VCOM (reset level). Secure 1.0 µsMIN at least. Sampling is possible at this time. Input the start pulse at this time. These characteristics are specified by load constants of 50 k Ω + 100 pF. (5) Internal sampling delay CLK SP1 SP2 DR0 to DR3 (input) DG0 to DG3 (input) DB0 to DB3 (input) td1 td1 td2 td2 Timing Duration Symbol Description CLK-sampling pulse delay td1 Delay time between CLK signal and rising edge of internal sampling pulse SPn. Input an analog image signal with a timing difference of td1 in order to secure a sufficient sampling period. Sampling pulse-CLK delay td2 Delay time between CLK signal and falling edge of internal sampling pulse. td1 is 22 ±5 ns and td2 is 14 ±5 ns (these are not guaranteed values). |
Similar Part No. - PD16602_15 |
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Similar Description - PD16602_15 |
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