LTC1840

8

1840f

LTC1840 Device Addressing

It is possible to configure the part to operate with any one

of nine separate addresses through the three state A0 and

A1 pins. Table 1 shows the correspondence of addresses

to the states of the pins:

Table 1. Device Addressing

LTC1840

2-Wire Bus Slave Address Bits

Device Address

(B7,B6,B5 = 111)

A0

A1

B4

B3

B2

B1

L

NC

0000

NC

H

0001

NC

NC

0010

H

NC

0011

LL0100

H

H

0101

NC

L0110

H

L0111

L

H

1000

For the A0 and A1 lines, L refers to a grounded pin, H is a

Bits B7, B6 and B5 of the address are hardwired to 111.

Register Addresses and Contents

Fault conditions are cleared by the action of writing to the

fault register, but the data byte from the write command is

not actually loaded into the register.

A TACHA/B FLT (fault) bit will be high if the corresponding

TACHA/B FLTEN bit in the status register has been set high

and the corresponding TACHA/B counter has overflowed

its maximum count of 255. These faults are latched

internally and must be cleared by writing to the fault

register or by setting TACHA/B FLTEN low. The fault will be

reasserted if the counter is still in overflow after a write to

the fault register. The TACH FLT bits power-up in the low

state.

The blast and timer bits become high after blasting and

serial access time-out events, respectively.

A high GPIOX FLT bit reflects that the GPIOX pin has

caused a fault condition; to do so, the pin must be enabled

as fault producing in the GPIO setup register (GPIOX

FLTEN set high) and the logic state of the pin must change

after the enable. The fault is latched internally and must be

cleared through software by writing to the fault register or

by setting GPIOX FLTEN low; a change in the state of the

GPIOX pin from its state at the point of the fault register

being written will cause another fault to be signalled.

OPERATIO

Register

Register

Name

Address

Data Byte

(R/W)

R2 R1 R0

D7

D6

D5

D4

D3

D2

D1

D0

FAULT

000

TACHA FLT

TACHB FLT

Blast

Timer

GPI04 FLT

GPI03 FLT

GPI02 FLT

GPI01 FLT

(0)

(0)

(0)

(0)

(0)

(0)

(0)

(0)

STATUS

001

TACHA FLTEN TACHB FLTEN

DIV1

DIV0

*See Note 2

(0)

(0)

(0)

(0)

(0/1)

(0)

(0)

(1)

DACA

010

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

(0)

(0)

(0)

(0)

(0)

(0)

(0)

(0)

DACB

011

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

(0)

(0)

(0)

(0)

(0)

(0)

(0)

(0)

TACHA

100

Cnt A7

Cnt A6

Cnt A5

Cnt A4

Cnt A3

Cnt A2

Cnt A1

Cnt A0

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

TACHB

101

Cnt B7

Cnt B6

Cnt B5

Cnt B4

Cnt B3

Cnt B2

Cnt B1

Cnt B0

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

GPIO Data

110

GPIO4 Pin

GPIO3 Pin

GPIO2 Pin

GPIO1 Pin

GPIO4 Reg

GPIO3 Reg

GPIO2 Reg

GPIO1 Reg

(N/A)

(N/A)

(N/A)

(N/A)

(1)

(1)

(1)

(1)

GPIO Setup

111

GPIO4 BLNK

GPIO3 BLNK

GPIO2 BLNK

GPIO1 BLNK

GPIO4 FLTEN GPIO3 FLTEN GPIO2 FLTEN GPIO1 FLTEN

(0)

(0)

(0)

(0)

(0)

(0)

(0)

(0)

Table 2. LTC1840 Register Address and Contents

Note 1: Number in ( )signifies default bit status upon power-up.

Note 2: State of bit depends on slave address used.