7

LT6301

sn6301 6301f

APPLICATIO S I FOR ATIO

The LT6301 is a high speed, 200MHz gain bandwidth

product, quad voltage feedback amplifier with high output

current drive capability, 500mA source and sink. The

LT6301 is ideal for use as a line driver in xDSL data

communication applications. The output voltage swing

has been optimized to provide sufficient headroom when

operating from

±12V power supplies in full-rate ADSL

applications. The LT6301 also allows for an adjustment of

the operating current to minimize power consumption. In

addition, the LT6301 is available in a small footprint

surface mount package to minimize PCB area.

To minimize signal distortion, the LT6301 amplifiers are

decompensated to provide very high open-loop gain at

high frequency. As a result each amplifier is frequency

stable with a closed-loop gain of 10 or more. If a closed-

loop gain of less than 10 is desired, external frequency

compensating components can be used.

Setting the Quiescent Operating Current

Power consumption and dissipation are critical concerns

in multiport xDSL applications. Two pins, Shutdown

(SHDN) and Shutdown Reference (SHDNREF), are provided

to control quiescent power consumption and allow for the

complete shutdown of the drivers. The quiescent current

should be set high enough to prevent distortion induced

errors in a particular application, but not so high that power

is wasted in the driver unnecessarily. A good starting point

to evaluate the LT6301 is to set the quiescent current to

10mA per amplifier. Pins 4 and 5 set the current for ampli-

fiers A and B and Pins 10 and 11 set the current for amplifers

C and D. Each amplifier pair should be controlled separately.

The internal biasing circuitry is shown in Figure 1. Ground-

ing the SHDNREF pin and directly driving the SHDN pin with

a voltage can control the operating current as seen in the

Typical Performance Characteristics. When the SHDN pin

is less than SHDNREF + 0.4V, the driver is shut down and

consumes typically only 100

µA of supply current and the

outputs are in a high impedance state. Part to part varia-

tions, however, will cause inconsistent control of the qui-

escent current if direct voltage drive of the SHDN pin is used.

ways provides a much more predictable control of the

quiescent supply current. Figure 2 illustrates the effect on

and the approximate design equations. Figure 3 illustrates

Either approach is equally effective.

Figure 1. Internal Current Biasing Circuitry

2k

SHDN

SHDNREF

TO

START-UP

CIRCUITRY

1k

6301 F01

TO AMPLIFIERS

BIAS CIRCUITRY

2I

I

2I

5I

2

5

0

10

20

30

5

15

25

10

6301 F02

7

40

70

100

130

160

190

SHDN

SHDNREF

• 25.6 – 2k

• 25.6

≈