DDR memory interface

AN2797

6/23

Doc ID 14841 Rev 1

2

DDR memory interface

2.1

DRAM power decoupling

A low impedance wide bandwidth power delivery network (PDN) is critical for the proper

operation of high-speed ICs such as SPEAr and DDR memory. If the PDN impedance is too

high or does not have sufficient bandwidth, this affects the logic performance, resulting in

ground and rail bounce, slower rise/fall times of both I/O and internal logic, which in turn

result in delayed timing of events. These timing delays, from inadequate ground and power,

subtract directly from the specified timing budget, which in turn can result in failure of the

interface.

To achieve a low impedance, wide bandwidth power delivery network, it is critical to use

appropriate decoupling capacitors and capacitor layout. A large portion of the power

delivery network's frequency spectrum is above the series resonant frequency of the

decoupling capacitors, where they are inductive. The PCB layout for decoupling capacitors

is also inductive, and is a larger inductance than the capacitor itself. It is necessary to select

capacitors with low inherent inductance (small package size), a lossy dielectric, and a PCB

layout that provides the lowest possible inductance. For IC core voltage and high-speed I/O

supplies (like DDR), as many capacitors should be used as can fit in the space available.

This adds many parallel paths, reducing the overall inductance seen by the IC. A small

capacitor package size and a small layout can be used to enable this.

Capacitors: Use 0402 package size to minimize the mounting inductance. The small 0402

package frees more board space, which is essential in high-density areas for more

decoupling capacitors and signal routing. A capacitance value of 100 nF or larger is

recommended, with X7R or X5R dielectric. Do not use Y5V dielectric for decoupling of mid-

frequency applications. A few capacitors of smaller capacitance value probably may be

necessary to suppress plane resonance. The correct value(s) to use for controlling

resonance is very dependent on the board layout and stack up and must be determined

individually for each unique PC board.

Decoupling capacitor layout: The layout of decoupling capacitors is extremely important

to minimize the induction loop formed between the capacitor and the IC power and ground

balls. The vias should be placed on the side of the capacitor lands, not the ends. The vias

should be located at minimum keepout distance and connected to the capacitor lands with a

wide trace - at least as wide as the via pad. Vias of opposite polarity should be placed as

close together as possible (minimum keepout distance) and vias of the same polarity should

be kept separated as much as possible. Following these layout guidelines can reduce the

capacitor mounting induction loop by 50% or more over a layout with vias at the end of the

capacitor lands. This is a very significant improvement, and is free. If space allows, a second

pair of vias on the opposite side of the capacitor may be added to reduce the inductance

further.