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AN2647 Datasheet(PDF) 11 Page - STMicroelectronics |
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AN2647 Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 34 page AN2647 Interfacing with asynchronous memory 11/34 1.1.2 Non-multiplexed EMI bus configuration The 8-bit non-multiplexed bus has a different set of bus signal, port assignment and bus timing. Table 2 shows the non-multiplexed bus signal pin assignments. The non-multiplexed bus has 16 address lines and this limits the memory bank size to no more than 64 KB. Figure 6. shows a typical non-multiplexed bus connection to an 8-bit Cypress SRAM. Table 2. Non-multiplexed bus signals Figure 6. Non-multiplexed bus port connection Read bus cycle timing configuration Figure 7 shows a typical Read Bus Cycle. All bus timings are referenced to the internal BCLK clock signal. BCLK clock is only available on an external pin for various usage on the 144 pin BGA package. Signal name Pin / Port assignment Signal description D0-D7 Port 8 Data bus D0-D7 A0-A7 Port 7 Address A0-A7 A8-A15 Port 9 Address A8-A15 Read EMI_RDn Read signal Write EMI_BWRn Write signal, same as EMI_WRLn CS0-CS3 Port 0(P0.4-P0.7) or Port 5 (P5.4-P5.7) or One chip select for each of the 4 Memory Banks.Can be assigned to any of these two ports. |
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