Port0 startup configuration

AN2595 - Application note

10/20

Table 2.

Clock options on PORT0 P0H.5/.7 for devices with low-power oscillator

P0H.7

P0H.6

P0H.5

CPU frequency

External clock

1.

The external clock input range refers to a CPU clock range of 1...64 MHz.

Notes

11

1

4 to 8 MHz

Default configuration

11

0

5.3 to 8 MHz

10

1

4 to 8 MHz

10

0

6.4 to 8 MHz

01

1

1 to 64 MHz

2.

The maximum input frequency depends on the duty cycle of the external clock signal (refer to the latest

datasheet).

01

0

4 to 6.4 MHz

00

1

4 to 8 MHz

3.

The limit on input frequency is 4 to 8 MHz since the usage of the internal oscillator amplifier is required.

Also, when the PLL is not used and the CPU clock corresponds to FXTAL/2, an external crystal or

resonator should be used: It is not possible to force any clock with an external clock source.

00

0

4 MHz

Table 3.

Clock options on PORT0 P0H.5 /.7 for devices with wide-swing oscillator

P0H.7

P0H.6

P0H.5

CPU frequency

External clock

1.

The external clock input range refers to a CPU clock range of 1...64 MHz.

Notes

11

1

4 to 8 MHz

Default configuration

11

0

5.3 to 10.6 MHz

10

1

4 to 8 MHz

10

0

6.4 to 12 MHz

01

1

1 to 64 MHz

2.

The maximum input frequency depends on the duty cycle of the external clock signal (refer to the latest

datasheet).

01

0

4 to 6.4 MHz

00

1

4 to 12 MHz

3.

The limit on input frequency is 4 to 12 MHz since the usage of the internal oscillator amplifier is required.

Also when the PLL is not used and the CPU clock corresponds to FXTAL/2, an external crystal or resonator

shall be should be used: It is not possible to force any clock with an external clock source.

00

0

4 MHz