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AN2202 Datasheet(PDF) 6 Page - STMicroelectronics |
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AN2202 Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 12 page 3 STR73x low power modes AN2202 6/12 3 STR73x low power modes 3.1 Low power mode characteristics The STR73x low power modes are summarized in the following table: Table 1. STR73x low power modes Note: 1 Refer to Figure 3 for the definition of the various clocks (MCLK, CLK1, CLK2, CLK2/16, RC). 3.2 Guidelines for entering/exiting low power modes 3.2.1 SLOW mode To enter SLOW mode, MCLK must be configured as CLK2 or CLK2/16. When using these clock settings, the PLL can be disabled by writing ‘111’ in the DX[2:0] bits in the PRCCU_PLLCR register. Table 2. SLOW mode selection Note: 1 CSU_CKSEL is bit 0 in register PRCCU_CFR. 2 CK2_16 is bit 3 in register PRCCU_CFR Power mode Description SLOW - PLL off and MCLK1) = CLK2 or CLK2/16 - Free running PLL Wait For Interrupt (WFI) - Core stopped (MCLK off) - Wake-up by interrupts acknowledged by the interrupt controller (EIC) - MCU state retained (context restored after wakeup) Low Power WFI (LPWFI) - Core stopped (MCLK off) - Peripherals running at slow clock: CLK2/16 - Wake-up by interrupts acknowledged by the EIC - MCU state retained STOP - Core and peripherals stopped (MCLK off) - Wake-up by the configured external wake-up lines - MCU state retained HALT - Oscillators stopped - Wake up is only possible by means of external reset (H/W pin) or LVD reset (Power-on) as the RC oscillator is off MCLK CSU_CKSEL1) CK2_16 2) FREEN 3) CLK2 0 1 0 CLK2/16 x 0 0 Free running PLL 1 1 1 |
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