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LTC4064 Datasheet(PDF) 6 Page - Linear Technology |
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LTC4064 Datasheet(HTML) 6 Page - Linear Technology |
6 / 16 page LTC4064 6 sn4064 4064fs PI FU CTIO S CHRG (Pin 1): Open-Drain Charge Status Output. When the battery is being charged, the CHRG pin is pulled low by an internal N-channel MOSFET. When the charge current drops to 10% of the full-scale current, the N-channel MOSFET latches off and a 30µA current source is con- nected from the CHRG pin to ground. The C/10 latch can be cleared by grounding the SHDN pin, momentarily, or toggling VCC. When the timer runs out or the input supply is removed, the current source is disconnected and the CHRG pin is forced high impedance. VCC (Pin 2): Positive Input Supply Voltage. When VCC is within 35mV of VBAT or less than the undervoltage lockout threshold, the LTC4064 enters sleep mode, dropping IBAT to less than 3µA. VCC can range from 4.25V to 6.5V. Bypass this pin with at least a 4.7µF ceramic capacitor to ground. FAULT (Pin 3): Open-Drain Fault Status Output. The FAULT open-drain logic signal indicates that the charger has timed out under trickle charge conditions or the NTC comparator is indicating an out-of-range battery tempera- ture condition. If VBAT is less that 2.48V, trickle charging begins whereby the charge current drops to one tenth of its programmed value and the timer period is reduced by a factor of four. When one fourth of the timing period has elapsed, if VBAT is still less than 2.48V, trickle charging stops and the FAULT pin latches to ground. The fault can be cleared by toggling VCC, momentarily grounding the SHDN pin or pulling the BAT pin above 2.48V. If the NTC comparator is indicating an out-of-range battery tempera- ture condition, the FAULT pin will pull to ground until the temperature returns to the acceptable range. TIMER (Pin 4): Timer Capacitor. The timer period is set by placing a capacitor, CTIMER, to ground. The timer period is: Time (Hours) = (CTIMER • 3 hr)/(0.1µF) Short the TIMER pin to ground to disable the internal timer function. GND (Pins 5, 11): Ground. The exposed backside of the package is also ground and must be soldered to the PC board for maximum heat transfer. NTC (Pin 6): Input to the NTC (Negative Temperature Coefficient) Thermistor Temperature Monitoring Circuit. With an external 10kΩ NTC thermistor to ground and a 1% resistor to VCC, this pin can sense the temperature of the battery pack and stop charging when it is out of range. When the voltage at this pin drops below (0.5)•(VCC) at hot temperatures or rises above (0.875)•(VCC) at cold, charg- ing is suspended and the internal timer is frozen. The CHRG pin output status is not affected in this hold state. The FAULT pin will be pulled to ground, but not latched. When the temperature returns to an acceptable range, charging will resume and the FAULT pin is released. The NTC feature can be disabled by grounding the NTC pin. PROG (Pin 7): Charge Current Program and Charge Cur- rent Monitor Pin. The charge current is programmed by connecting a resistor, RPROG to ground. When in con- stant-current mode, the LTC4064 servos the PROG pin voltage to 1.5V. In all modes the voltage on the PROG pin can be used to measure the charge current as follows: IBAT = (VPROG/RPROG) • 1000. SHDN (Pin 8): Shutdown Input Pin. Pulling the SHDN pin to ground will put the LTC4064 into standby mode where the BAT drain current is reduced to less than 3µA, and the supply current is reduced to less than 25µA. For normal operation, pull the SHDN pin up to VCC. BAT (Pin 9): Charge Current Output. A bypass capacitor of at least 1µF with a 1Ω series resistor is required to keep the loop stable when the battery is not present. A precision internal resistor divider sets the final float potential on this pin. The internal resistor divider is disconnected in sleep and shutdown mode. ACPR (Pin 10): Open-Drain Power Supply Status Output. When VCC is greater than the undervoltage lockout thresh- old and at least 35mV above VBAT, the ACPR pin will pull to ground. Otherwise, the pin is high impedance. |
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