10

LTC3405A

3405afa

APPLICATIO S I FOR ATIO

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of the

loss dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve at

very low load currents can be misleading since the actual

power lost is of no consequence as illustrated in Figure 4.

continuous mode, the average output current flowing

through inductor L is “chopped” between the main

switch and the synchronous switch. Thus, the series

resistance looking into the SW pin is a function of both

(DC) as follows:

be obtained from the Typical Performance Charateristics

output current.

losses and inductor core losses generally account for less

than 2% total additional loss.

Thermal Considerations

In most applications the LTC3405A does not dissipate

much heat due to its high efficiency. But, in applications

where the LTC3405A is running at high ambient

temperature with low supply voltage and high duty

cycles, such as in dropout, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 150°C,

both power switches will be turned off and the SW node

will become high impedance.

To avoid the LTC3405A from exceeding the maximum

junction temperature, the user will need to do some

thermal analysis. The goal of the thermal analysis is to

determine whether the power dissipated exceeds the

maximum junction temperature of the part. The tempera-

ture rise is given by:

is the thermal resistance from the junction of the die to the

ambient temperature.

Figure 4. Power Lost vs Load Current

LOAD CURRENT (mA)

0.1

10

1000

1

0.1

0.01

0.001

0.0001

3405A F04

1

100

the DC bias current as given in the electrical character-

istics and the internal main switch and synchronous

switch gate charge currents. The gate charge current

results from switching the gate capacitance of the

internal power MOSFET switches. Each time the gate is

switched from high to low to high again, a packet of

internal top and bottom switches. Both the DC bias and

their effects will be more pronounced at higher supply

voltages.