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AN1753 Datasheet(PDF) 7 Page - STMicroelectronics |
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AN1753 Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 22 page DocID9986 Rev 2 7/22 AN1753 ST7FLITE0 configuration 3 ST7FLITE0 configuration 3.1 Clock source This application is implemented using an ST7FLITE0 device with an 8 MHz internal clock. PLL * 8 is used to generate this 8 MHz clock. 3.2 Input initialization Two pins of the ST7FLITE0 are used: • PA3: pin of PortA • PA7: pin of PortA with interrupt Pin PA3 is a normal input/output port pin with no alternate function, used for transmission. During the initialization, it is configured as an output. Pin PA7 is a normal input/output port pin with no alternate function, used for data receive. During the initialization, it is configured as an input. While in receive mode, at start, the same pin is used with interrupt enabled (“ei1”) to sense the start bit. So this pin is configured with “pull up interrupt input” by setting PADDR to 0 & PAOR to 1. To set the interrupt sensitivity “Falling edge only”, you have to set IS11=1 & IS10=0 in the EICR register. Refer to the device datasheet for a detailed description of the I/O and interrupt control registers. 3.3 Auto-reload timer register configuration The AT timer is based on a free running 12-bit upcounter with 12-bit auto reload register (ATR). Apart from this, it also includes other functions such as PWM signal generator, Output Compare Function, etc. The “Output Compare” function is used for this application. To use it, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register. The software must then write a 12-bit value in the DCR0H and DCR0L registers. When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is generated, provided that the CMPIE bit is set. The registers that are used in the application note are: TIMER CONTROL STATUS REGISTER (ATCSR): • CK1, CK0: select the clock frequency of the counter. – For fcounter = fcpu, set CK1=1 and CK0=0 • CMPIE: allows to mask the interrupt generation when the CMPF bit is set: – 0: the CMPF interrupt is disabled – 1: the CMPF interrupt is enabled CMPIE OVFIE OVF CK0 CK1 0 0 0 |
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