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R1EX24128BSAS0A Datasheet(PDF) 7 Page - Renesas Technology Corp |
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R1EX24128BSAS0A Datasheet(HTML) 7 Page - Renesas Technology Corp |
7 / 18 page R1EX24128BSAS0A/R1EX24128BTAS0A Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation (See start condition and stop condition). Stop Condition A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in a internally-timed write cycle to the memories. After the internally-timed write cycle which is specified as tWC, the device enters a standby mode (See write cycle timing). Start Condition and Stop Condition SCL SDA (in) Stop condition Start condition SCL SDA IN SDA OUT 12 8 9 Acknowledge out Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to acknowledge after receiving the device address word. After sending read data, the EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge, it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending read data. Acknowledge Timing Waveform R10DS0006EJ0100 Rev.1.00 Page 7 of 16 Aug. 04, 2010 |
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