5

LTC1564

1564fa

TYPICAL PERFOR A CE CHARACTERISTICS

PI FU CTIO S

OUT (Pin 1): Analog Output. In normal filtering, this is the

output of an internal operational amplifier and is capable

of swinging essentially to any voltage between the power

designed to drive a nominal load of 5k and 50pF. For

lowest signal distortion it should be loaded as lightly as

possible. The output can drive lower resistances than 5k,

but distortion may increase, and the output current will

limit at approximately

±10mA. Capacitances higher than

50pF should be isolated by a series resistor of 500

Ω to

preserve AC stability. In the Mute state (F code 0000 or

RST = 0), the output operates as in normal filtering but the

gain from the IN pin becomes zero and the output noise is

reduced. In the shutdown state (EN = 1 or EN open

circuited), most of the circuitry in the LTC1564 shuts off

and the OUT pin assumes a high impedance state.

pins should be bypassed with 0.1

µF capacitors to an

adequate analog ground plane using the shortest possible

wiring. Electrically clean supplies and a low impedance

ground are important for the high dynamic range and high

stopband suppression available from the LTC1564 (see

further details under AGND). Low noise linear power

supplies are recommended. Switching supplies are not

recommended because of the inevitable risk of their

switching noise coupling into the signal path, reducing

dynamic range.

EN (Pin 3): CMOS-Level Digital Chip Enable Input. Logic 1

or open circuiting this pin causes a shutdown mode with

reduced supply current. The active circuitry in the LTC1564

shuts off and its output assumes a high impedance state.

If F and G bits are latched (CS/HOLD = 1) during the

shutdown state, the latch will retain its contents.

A small pull-up current source at the EN input causes the

LTC1564 to be in shutdown state if the EN pin is left open.

or optionally 0V with

±5V supplies) for normal filter

operation.

CS/HOLD (Pin 4): CMOS-Level Digital Enable Input for the

Latch Holding F and G Bits. Logic 0 makes the latch

transparent so that the F and G inputs directly control the

filter’s cutoff frequency and gain. Logic 1 holds the last

values of these inputs prior to the transition. This pin floats

current source (see Electrical Characteristics, Note 5).

F3, F2, F1, F0 (Pins 5, 6, 7, 8): CMOS-Level Digital

Frequency Control (“F Code”) Inputs. F3 is the most

significant bit (MSB). These pins program the LTC1564’s

THD + Noise vs Input Voltage

–80

–60

–50

–30

–20

0.001

0.1

1

10

1564 G12

–100

0.01

–40

–70

–90

3V SUPPLY

5V SUPPLY

±5V SUPPLY

BASEBAND GAIN SETTING

2

1

10

100

4

8

1564 G13

1

16

FREQUENCY (Hz)

–60

–40

–30

–10

10

0.1k

10k

100k

1M

1564 G14

–80

1k

–20

–50

–70

0

NEGATIVE SUPPLY

µF

POSITIVE SUPPLY

µF

Noise vs Frequency

and Gain Settings

Power Supply Rejection

vs Frequency