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AN1042 Datasheet(PDF) 2 Page - STMicroelectronics |
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AN1042 Datasheet(HTML) 2 Page - STMicroelectronics |
2 / 8 page 2/8 ST7 ROUTINE FOR I2C SLAVE MODE MANAGEMENT 1.3 TRANSFER SEQUENCING Figure 1. I2C Slave Transfer Sequencing Diagram Legend:S=Start, P=Stop, A=Acknowledge, NA=Non-Acknowledge, EVx=Event (with interruptif ITE=1). EV1: EVF=1, ADSL=1, cleared by reading SR1 register. EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV3_1: EVF=1, AF=1, cleared by reading SR1 register. EV4: EVF=1, STOPF=1, cleared by reading SR2 register. In blue are events sent by the master whereas blank ones are events sent by the slave. These frames are sequential and as the SDA line is bidirectional, this line is held sometimes by the master and sometimes by the slave. 1.4 SLAVE EVENT FLAGS AND INTERRUPT GENERATION Figure 2. Slave Interrupt Events Diagram 7-bit Slave receiver: 7-bit Slave transmitter: 10-bit Slave receiver: 10-bit Slave transmitter: 1 S Address A Data1 A Data2 A ..... DataN A P EV1 EV2 EV2 EV2 EV4 S Address A Data1 A Data2 A ..... DataN NA P EV1 EV3 EV3 EV3 EV3-1 EV4 S HeaderA Address A Data1 A ..... DataN A P EV1 EV2 EV2 EV4 Sr Header A Data1 A .... . DataN AP EV1 EV3 EV3 EV3-1 EV4 EVF INTERRUPT ITE * * EVF can also be set by EV6 or an error from the SR2 register. BTF ADSL BERR AF STOPF 2 S |
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