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AN437 Datasheet(PDF) 5 Page - STMicroelectronics |
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AN437 Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 18 page AN437 Snubber circuit functions and drawback 5/18 1.3 Immunity to fast voltage transient improvement Electrical noise may appear on the mains and generates across the TRIAC fast voltage variations, as described in IEC 61000-4-4 standard. Fast voltage variations can create a gate current (IG), due to the junction capacitance between A2 and the gate, and could trigger the TRIAC. The maximum rate of rise of off- state voltage that a TRIAC is able to withstand without turning on is called the static dV/dt. A spurious triggering due to static dV/dt is not dangerous for a component. The aim of the snubber circuit is to reduce the static dV/dt at a lower level than the dV/dt specified in the datasheet to avoid spurious triggering. An RC snubber circuit improves the TRIAC immunity against fast voltage transients. For example, regarding to the standard IEC 61000-4-4, a Z0109 standard TRIAC has a typical immunity level of about 0.7 kV, without any snubber circuit. With a snubber circuit (1 nF and 47 Ω), the Z0109 immunity level can reach 4.0 kV. Designers must manage the following trade-off to choose the suitable RC snubber circuit: ● Reduce dV/dt rates: the snubber capacitance must be high and the snubber resistance must be low; ● Reduce dI/dt rate at turn-on (refer to Section 1.4): the snubber capacitance must be low and the snubber resistance must be high. 1.4 Turn-on stress due to snubber circuit discharge The snubber circuit design can lead to low resistance value. However, the snubber resistor reduces the rate of current rise at turn-on (dI/dtON) during the capacitor discharge. An higher dI/dtON than the dI/dt specified in the datasheet may damage the TRIAC. The rate of current rise is directly proportional to the initial capacitance voltage and inversely proportional to the series inductances of the board and the snubber resistor. The rate of current rise depends also on the turn-on speed of the TRIAC, the triggering quadrants and the gate current amplitude. So, there is no simple way to predict the rate of current rise. Usually, the inductance of the circuit layout is very low, in the range of few nH. Indeed, to optimize the snubber circuit efficiency, the snubber circuit must be located very close to the TRIAC (tracks length lower than 2 cm). From datasheet specifications, there are three ranges of maximum dI/dt: ● dI/dt = 20 A/µs: for low current rating of TRIACs (0.8 A and 1 A). ● dI/dt = 50 A/µs: for the other TRIACs (4 A up to 40 A). ● dI/dt = 100 A/µs: for some ACSTs (6 A up to 12 A). To keep the dI/dtON below 50 A/µs for TRIACs and below 100 A/µs for ACSTs, the snubber resistance must be typically higher than 47 Ω (refer to Figure 6). For a 20 A/µs maximum dI/dt, the minimum resistance value is about 620 Ω. Therefore, depending on the component used, some tests should be performed to define accurately the minimum resistance value. |
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