AN4192 datasheet(6/47 Pages) STMICROELECTRONICS

Part #	AN4192

Description	In the latest generation of CPUs for modern desktop and notebook platforms

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Synchronous buck converter: a brief introduction

AN4192

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Doc ID 023820 Rev 1

1

Synchronous buck converter: a brief introduction

The basic topology of a single-phase synchronous buck converter (SBC) is shown in

Figure 1; SW1 is the main (or high-side) FET, SW2 is the synchronous (or low-side) FET, L

and C are the output filters.

Figure 1.

Synchronous buck converter simplified schematic

Comparing this topology to the standard buck converter, the main difference is the

synchronous rectifier (SW2) instead of the free-wheeling diode; as VDS(on) < VF,DIODE, a

strong reduction of the ON-state losses is guaranteed.

SW1 and SW2 are driven in a “synchronous” way: in other words, the control IC generates

the gate driving signals, avoiding the simultaneous conduction of the two FETs (cross-

conduction or shoot-through). So, when SW1 is in the ON-state, SW2 is turned off and vice

versa. Obviously, to prevent HS and LS gate-source voltages overlapping and any cross-

conduction issue, there are some time intervals (fixed by the control IC) where HS and LS

FETs are in the OFF-state (deadtime).

In Figure 2, the typical waveforms of a single-phase synchronous buck converter are

represented. When the HS FET (SW1) is turned on, its drain current rises with a positive

slope:

during HS ton. When HS switches off, the LS FET remains in the HOLD state: the energy

stored in L can't become zero immediately, so it freewheels through the LS body-drain diode

(from source to drain, VDS,LS = -0.7 V). When the LS turns on, the load current diverts from

the body diode to the LS channel, with a negative slope:

AM16445V1

dI

L

dt

--------

V

in

V

core

–

L

----------------------------

=

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