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LTC1658 Datasheet(PDF) 7 Page - Linear Technology |
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LTC1658 Datasheet(HTML) 7 Page - Linear Technology |
7 / 12 page 7 LTC1658 OPERATIO Serial Interface The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first. The DAC register loads the data from the shift register when CS/LD is pulled high. The clock is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. The input word must be 16 bits wide. The last two bits are don’t cares. The buffered output of the 16-bit shift register is available on the DOUT pin which swings from GND to VCC. Multiple LTC1658s may be daisy-chained together by connecting the DOUT pin to the DIN pin of the next chip while the clock and CS/LD signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips then the CS/LD signal is pulled high to update all of them simultaneously. Voltage Output The LTC1658 rail-to-rail buffered output can source or sink 5mA over the entire operating temperature range while pulling to within 400mV of the positive supply voltage or ground. The output swings to within a few millivolts of ei- ther supply rail when unloaded and has an equivalent out- put resistance of 40 Ω,at5VVCC,whendrivingaloadtothe rails. The output can drive 1000pF without going into os- cillation. The output swings from 0V to the voltage at the REF pin, i.e., there is a gain of 1 from REF to VOUT. Please note, if REF is tied to VCC the output can only swing to (VCC – VOS). See Applications Information. |
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