7

LTC1329-10/

LTC1329-50/LTC1329A-50

Standard 3-Wire Mode (Figure 3)

Refer to the Serial Interface Operating Sequence in Figure

1. When operating in 3-wire mode, the LTC1329-10/

LTC1329-50/LTC1329A-50 will interface directly with most

standard 3- or 4-wire serial interface systems. The clock

(CLK) input synchronizes the data transfer with each input

bit captured at the rising edge of CLK and each output data

pin out of three-state. The serial 8-bit data representing the

neously, the previous DAC setting is shifted out of the

CS transfers the data from the input shift register into the

DAC register. The DAC output assumes the new value and

1

2

SHDN

CLK

CS

8

7

SHDN

CLK

LTC1329

GND

CS

1329 F03

3

4

6

5

0.1

µF

FOR HALF DUPLEX DATA TRANSFER

Figure 3. 3-Wire Mode; Serial Interface

1-Wire Interface (Pulse Mode, Figure 4)

In 1-wire pulse mode, each rising edge at CLK increments

the upper six bits of the DAC register by one count. When

incramented beyond 11111100B, the counter rolls over

and sets the DAC to the minimum value (00000000B). In

this way, a single pulse applied to CLK increases the DAC

output by a single 4-LSB step and 63 pulses decrease the

DAC output by one step. The last two LSBs are always zero

in pulse mode.

To configure the LTC1329-10/LTC1329-50/LTC1329A-50

1

2

SHDN

CLK

8

7

SHDN

CLK

LTC1329

GND

CS

1329 F04

3

4

6

5

0.1

µF

Figure 4. Pulse Mode: Increment Only

(1-Wire Control by CLK)

2-Wire Interface (Pulse Mode, Figure 5)

In 2-wire pulse mode, a logic HIGH at UP/DN programs the

DAC register to increment and each rising edge at CLK

increments the upper six bits of the register by one count.

Similarly, a logic LOW at UP/DN set the DAC register to

decrement and a rising edge at CLK decrements the upper

six bits of the register by one count. Each count in 2-wire

mode changes the DAC output by a single four LSB step.

The DAC register stops incramenting at 11111100B and

stops decrementing at 00000000B and will not roll over in

2-wire pulse mode. The last two LSBs are always zero in

pulse mode.

To configure the LTC1329-10/LTC1329-50/LTC1329A-50

pin low at least once during power-up.

1

2

SHDN

CLK

UP/DN

8

7

SHDN

CLK

LTC1329

GND

CS

1329 TA04

3

4

6

5

0.1

µF

Figure 5. Pulse Mode; Increment/Decrement

(2-Wire Control by CLK and UP/DN)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.